Implements the Verilog Language Extension for Visual Studio Editor versions 2015, 2017, and 2019.

Download & Sources

#verilog #VisualStudio #SyntaxHiglighter

Experimental High Level Synthesis (HLS) from prototype based object oriented scripting language (Karuta) to RTL (Verilog) which might become useful for FPGA development. Project designed its own language Karuta just only for RTL design instead of reusing existing languages.
>800 commits

Some of following features are incorporated in the language constructs to make it easy to use:

∙ Prototype based object system to model design structures
∙ Flexible data types
◦ Integer with width. Custom operators for defined data types like FP16
∙ Communication primitives
◦ Threads, mailboxes, channels and so on
◦ AXI, RPC like handshake, GPIO, embedded verilog and so on
∙ HDL generators and optimizers
◦ Generates Verilog or HTML
◦ SSA based optimizers
◦ Scheduling and allocation based on device parameters

https://github.com/nlsynth/karuta

#HLS #Karuta #iroha #verilog

Did you know that Icarus Verilog includes a non-standard random number generator as a built-in?

$mti_random()
$mti_dist_uniform

These functions are similar to the IEEE1364 standard $random functions, but they use the Mersenne Twister (MT19937) algorithm. This is considered an excellent random number generator, but does not generate the same sequence as the standardized $random.

#iverilog #simulation #verilog #random #RNG

VHD2VL - free and opensource translator for synthesizable VHDL into Verilog 1995/2001. It does not support the full VHDL grammar - most of the testbench related features have been left out. Syntax and semantics are not carefully checked. vhd2vl assumes that the input is error-free.
Vhd2vl is written using lex (actually Flex), yacc (actually Bison), and C.

The most important VHDL constructs missing from this version are
◦ packages
◦ structures
◦ functions
◦ strings
◦ attributes

Project page + sources

#VHDL #Verilog #converter #translator #flex #bison

HDL Checker - a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer library VHDL files likely belong to, besides working out mixed language dependencies, compilation order, interpreting some compilers messages and providing some static checks.

https://github.com/suoto/hdl_checker

#HDL #checker #LINT #verilog #VHDL #SV #python

Mentor's Functional Verification Training Series contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use SystemVerilog, HDL, UVM, CDC, ModelSim/Questa to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.

FREE for a 30-day access (hurry up to checkout until April 30): https://www.mentor.com/training/courses/functional-verification-training-library
Use promo code ODT-WECARE2020__30

PS: only corporate email are applicable

#Mentor #onlinetraining #webinar #training #verilog #SV #verification #FPGA

elf2hex - converts ELF files to HEX files that are suitable for Verilog's readmemh.

Verilog test harnesses can't directly read ELF binaries but are instead required to be provided with a hexidecimal dump of a particular width and depth. This project allows users to easily create these files.

./elf2hex [-h] --bit-width BIT_WIDTH --input IN.ELF [--output OUT.HEX]

◦ https://github.com/sifive/elf2hex

#ELF #HEX #memory #init #verilog

svlint - SystemVerilog linter a tool that providing some static checks (with rule based system).

▫️Source
▫️Rule plugin

#HDL #checker #LINT #verilog #SV #rust
@fpgasic

Vim plugin to work easier with Verilog & SystemVerilog

https://github.com/dpretet/vim-veritoolbox

#vim #vi #verilog #SV #python
@fpgasic

BTW, you can find a huge collection of RTL sources on this channel.

Feel free to join and share!
t.me/ipcores

Verilog Template for VS Code Remote Development

Verilog template which is easy to develop, using VS Code Remote Development. It uses Icarus Verilog, GTKWave, and Docker.

https://github.com/ha2zakura/verilog-template

#VScode #MS #verilog #SV #docker #icarus #gtkwave
@fpgasic

Verilog-HDL/SystemVerilog/Bluespec support for VS Code

Features
▫️ Syntax Highlighting
◦ Verilog
◦ SystemVerilog
◦ Bluespec SystemVerilog
◦ Vivado UCF constraints
◦ Synopsys Design Constraints
▫️Simple Snippets
▫️Linting support from:
◦ Icarus Verilog
◦ Vivado Simulation
◦ Modelsim
◦ Verilator
▫️Ctags Integration
◦ Autocomplete
◦ Document Symbols Outline
◦ Hover over variable declaration
◦ Go to Definition & Peek Definition
◦ Module Instantiation

https://github.com/mshr-h/vscode-verilog-hdl-support

#VScode #MS #verilog #SV #bluespec #lint snippets #syntax #icarus #modelsim #verilator
@fpgasic

OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

💾 https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic

TerosHDL 2.0.0 has been released. You can install it from VSCode market.

Features:
▫️Support for VHDL, Verilog, System Verilog
▫️Windows, Linux, Mac
▫️Simulators and tools support: Vivado, ModelSim, GHDL, Verilator, Icarus, VCS, Yosys, VUnit, cocotb, Diamond, Icestorm, ISE, Quartus, Radiant, Spyglass, Symbiflow, Trellis, Xcelium...
▫️Go to definition
▫️Hover
▫️Hiterachy viewer
▫️Dependencies viewer
▫️Syntax highlighting
▫️Template generator
▫️Automatic documentation
▫️Command line documenter
▫️Verilog/SV schematic viewer
▫️Errors linter
▫️Style linter: Verible
▫️Code formatting
▫️State machine viewer
▫️State machine designer
▫️Code snippets and grammar

💾 https://marketplace.visualstudio.com/items?itemName=teros-technology.teroshdl
📄 https://terostechnology.github.io/terosHDLdoc/

#verilog #vhdl #systemverilog #teroshdl #vunit #edalize #wavedrom #vscode
@fpgasic

Open-Source RISC-V GPGPU Project

Researchers have found a way to enable CUDA software toolkit support on a RISC-V GPGPU project called Vortex. The Vortex RISC-V GPGPU aims to provide a full-system RISC-V GPU based on RV32IMF ISA. That means 32-bit cores that can be scaled from 1-core to 32-core GPU designs. It supports OpenCL 1.2 graphics API, and today it got support for some CUDA action as well.

💾 https://t.me/ipcores/91
📄 https://www.tomshardware.com/news/risc-v-runs-cuda

#RISCV #GPGPU #GPU #FPGA #CUDA #Nvidia
@fpgasic

Verilog and SystemVerilog cheatsheet

#verilog #systemverilog #cheatsheet #digitaldesign
@fpgasic

openFPGALoader - Universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). openFPGALoader works on Linux, Windows and macOS.

openFPGALoader just released version 0.9.0 with most notable evolutions:
▫️libgpiod and XVC (XilinxInc Virtual Cable) support
▫️ORBTrace mini (DFU) and tang Primer 20K support
▫️GW2A, new Kintex models, ZynqMP Ultrascale (and Plus)

💾 https://github.com/trabucayre/openFPGALoader/releases/tag/v0.9.0
📄 https://trabucayre.github.io/openFPGALoader/

#jtag #loader #verilog #xvc #dfu #bitstream #ft2232
@fpgasic

Versatile list of HDL lint tools

📄 https://airhdl.com/blog/2017/02/08/fpga-lint-tools/
(updated August 2022)

#lint #linter #sv #verilog #vhdl
@fpgasic

sv2chisel - SystemVerilog to Chisel Translator

💾 Code
📄 Paper
📄 Features & Limitations

#SV #verilog #chisel #translator

@embedoka

VeriGen: A Large Language Model for Verilog Code Generation

The next step getting a Verilog fine-tuned LLM to generate the RTL; then we can kick-back & watch the whole SoC emerge autonomously. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.

💾 https://arxiv.org/abs/2308.00708

#verilog #sv #codegen #llm
@fpgasic