Wave Computing and Imperas introduce new MIPS Open Simulator MIPSOpenOVPsim - is a MIPS system architecture simulator, available at no cost, which implements a complete single-core CPU. MIPSOpenOVPsim is an entry ramp for software development, SoC testing and verification.

MIPSOpenOVPsim offers:
● A jump-start to software and firmware development during the SoC design cycle
● Early-stage implementation testing and Design Verification (DV) of MIPS CPU core designs
● Acceleration of compliance testing by providing a reference environment

MIPSOpenOVPsim helps SoC developers by providing a comprehensive testing platform for all MIPS Open specifications and extensions including:
● The MIPS 32 and 64-bit ISA Rev6 licensed under MIPS Open
● MIPS SIMD Extensions v1.0
● MIPS DSP Extensions
● MIPS Multi-Threading (MT)
● MIPS MCU
● microMIPS Architecture
● MIPS Virtualization (VZ)

Further details and download are available.

#MIPS #MIPSOpen #simulator #verification

Formal Verification with SymbiYosys and Yosys-SMTBMC
◦ Presentation Slides
◦ Examples

Investigating and Verifying Hardware Designs with Formal Open Source Tools
◦ Presentation Slides
◦ Examples

References:
==========

Yosys family:
◦ Yosys - a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains
◦ SymbiYosys - a front-end driver program for Yosys-based formal hardware verification flows

SAT and SMT solvers:
◦ Z3 Theorem Prover
◦ Yices2 SMT Solver
◦ Boolector
◦ ABC
◦ super_prove
◦ Avy

#Formal #Verification #SymbiYosys #Yosys #solver #publication #opensource

Mentor's Functional Verification Training Series contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use SystemVerilog, HDL, UVM, CDC, ModelSim/Questa to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.

FREE for a 30-day access (hurry up to checkout until April 30): https://www.mentor.com/training/courses/functional-verification-training-library
Use promo code ODT-WECARE2020__30

PS: only corporate email are applicable

#Mentor #onlinetraining #webinar #training #verilog #SV #verification #FPGA

SVUnit - an open-source test framework for ASIC and FPGA developers writing Verilog and SystemVerilog code.

SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.

💾 https://github.com/svunit/svunit
📄 http://www.agilesoc.com/svunit

#test #testbench #verification #sv #systemverilog #svunit
@fpgasic