FPG𝔸SIC
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FPG/A/SIC tips and tricks

#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera

PS: also might be intresting @ipcores
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vcd2wavedrom - a python script to transform a VCD file to wavedrom format. The tool have flexible config in json format.

vcd2wavedrom in fact is tb2svg tool that improve performance of prepare documentation.

https://github.com/Toroid-io/vcd2wavedrom

#vcd #wavedrom #waveform #testbench #waves #documentation
SVUnit - an open-source test framework for ASIC and FPGA developers writing Verilog and SystemVerilog code.

SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.

💾 https://github.com/svunit/svunit
📄 http://www.agilesoc.com/svunit

#test #testbench #verification #sv #systemverilog #svunit
@fpgasic
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VCD command line viewer for Windows, Linux and MacOS

Features:
▫️Outputs in YAML format
▫️Querying (unix pipe)
▫️Styling
▫️Auto-Refresh


💾 https://github.com/yne/vcd

#vcd #dump #waveform #testbench #waves #documentation
@fpgasic
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