PyMTL - an open-source python-based unified framework for multi-level hardware modeling and vertically integrated computer architecture research.

PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment for functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) modeling. PyMTL leverages the Python programming language to create a highly productive domain-specific embedded language for concurrent-structural modeling and hardware design.

A custom JIT engine automatically generates optimized C++ for CL and RTL models. To reduce the performance impact of the remaining unspecialized code, Sim JIT combines with an off-the-shelf Python interpreter with a meta-tracing JIT compiler (PyPy). Sim JIT+PyPy provides speedups of up to 72× for CL models and 200× for RTL models.

◦ Paper
◦ Tutorial + Examples
◦ Sources

#PyMTL #JIT #framework #python #modeling #verilator

BD_SHELL - is like a UNIX command line shell, but for manually writing and reading FPGA|ASIC registers on a 32bit Local Bus. Supports scripting of course and dumping register contents to a file. It works alongside SUMP2 as a diagnostic tool for chip bringup and debugging.

Fully cross platform compatible and much easier to maintain. BD_SHELL is part of "Backdoor" suite of tools for FPG/A/SIC diagnostics over a simple 2-pin FTDI cable for 1 Mbps UART communications using the Mesa Bus Protocol. The bd_server.py TCP server supports other links such a PCIe, SERDES, whatever you have that Python can talk to, bd_server.py can adapt to.

https://github.com/blackmesalabs/bd_shell

#debug #backdoor #FTDI #python #powershell

LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
#FPGA #NN #ML #LegUp #LLVM #DNN #Python #XLA #TensorFlow

HDL Checker - a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer library VHDL files likely belong to, besides working out mixed language dependencies, compilation order, interpreting some compilers messages and providing some static checks.

https://github.com/suoto/hdl_checker

#HDL #checker #LINT #verilog #VHDL #SV #python

Datasheet Scrubber - a utility that scrubs through large sets of PDF datasheets/documents in order to extract key circuit information. The information gathered is used to build a database of commercial off-the-shelf (COTS) IP that can be used to build larger SoC.

Datasheet Scrubber also define IP-XACT++, an extended version of IP-XACT, to encapsulate all the information needed for system generator, and port known IPs into the database. Doing this is really useful in finding the optimum SoC design based on user specifications.

Link:
◦ Description
◦ Sources

#datasheet #IPXACT #python #SoC #IP

How to logging FPGA resource usage by commit to commit?

Here good try to create a tool to track tranding LUT/FF/Freq by every commit:
https://github.com/mattvenn/logLUTs

#git #commit #stats #python

Vim plugin to work easier with Verilog & SystemVerilog

https://github.com/dpretet/vim-veritoolbox

#vim #vi #verilog #SV #python
@fpgasic

PyVCD - package writes Value Change Dump (VCD) files as specified in IEEE 1364-2005.
This tool also can generate GTKWave save files.

▫️ doc
▫️ src

#python #VCD #dump #GTKWave

🛠 IEEE P1735 decryptor for VHDL

This tool allow to recover full source code of encrypted module (provided you have an extracted private key from the software you're using). Usually software vendors do not care much about hiding their private keys. The decryption is done in two stages:

1️⃣ using the private key, a session key is decrypted using RSA decryption procedure
2️⃣ data block is decoded using this session key and AES-128-CBC decryption procedure

💾 https://github.com/dmitrodem/p1735_decryptor

#decryptor #python #IP #VHDL #P1735 #encryption #protection #Aldec
@fpgasic

fp2p - FPGA Port To Pin tool.

Utility for safe and reusable port to pin assignment in multi-board FPGA designs.

The implementation has two main goals, safety (check as many potential human mistakes as possible) and reusability (reuse connections mappings, defined in files, in multiple designs). It is fully declarative and programming language-agnostic from the users perspective.

https://github.com/m-kru/fp2p

#FPGA #pinout #pin #multiboard #python
@fpgasic

OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

💾 https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic

pysv - a lightweight Python library that allows functional models to be written in Python and then executed inside standard SystemVerilog simulators, via DPI.

Supported Simulators
▫️Cadence Xcelium
▫️Synopsys VCS
▫️Mentor Questa
▫️Vivado Simulator
▫️Verilator


💾 https://github.com/Kuree/pysv

#SV #systemverilog #python #simulation #cosimulation
@fpgasic

PipelineC - a C-like hardware description language (HDL) adding HLS(high level synthesis)-like automatic pipelining as a language construct/compiler feature.

💾 https://github.com/JulianKemmerer/PipelineC

#HLS #C #VHDL #python #pipelines #FPGA
@fpgasic

asciiwave - WaveDrom to ASCII art

💾 https://github.com/Wren6991/asciiwave

#waves #diagram #python #asciiart #wavedrom
@fpgasic