FPGš”øSIC
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FPG/A/SIC tips and tricks

#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera

PS: also might be intresting @ipcores
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PyMTL - an open-source python-based unified framework for multi-level hardware modeling and vertically integrated computer architecture research.

PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment for functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) modeling. PyMTL leverages the Python programming language to create a highly productive domain-specific embedded language for concurrent-structural modeling and hardware design.

A custom JIT engine automatically generates optimized C++ for CL and RTL models. To reduce the performance impact of the remaining unspecialized code, Sim JIT combines with an off-the-shelf Python interpreter with a meta-tracing JIT compiler (PyPy). Sim JIT+PyPy provides speedups of up to 72Ɨ for CL models and 200Ɨ for RTL models.

ā—¦ Paper
ā—¦ Tutorial + Examples
ā—¦ Sources

#PyMTL #JIT #framework #python #modeling #verilator
CLaaS - Custom Logic as a Service.
This solution, it significantly reduces the complexity of developing a hardware-accelerated application, bringing the platform within the reach of everyone, including startups, open-source enthusiasts and makers. With the framework, you can stream data directly between your custom FPGA kernel and application using standard websockets.

https://github.com/alessandrocomodi/fpga-webserver

#CLaaS #FPGA #web #framework #WebSocket #AWS