Did you know that Icarus Verilog includes a non-standard random number generator as a built-in?
These functions are similar to the IEEE1364 standard
#iverilog #simulation #verilog #random #RNG
$mti_random()
$mti_dist_uniform
These functions are similar to the IEEE1364 standard
$random functions, but they use the Mersenne Twister (MT19937) algorithm. This is considered an excellent random number generator, but does not generate the same sequence as the standardized $random.#iverilog #simulation #verilog #random #RNG
pysv - a lightweight Python library that allows functional models to be written in Python and then executed inside standard SystemVerilog simulators, via DPI.
Supported Simulators
▫️Cadence Xcelium
▫️Synopsys VCS
▫️Mentor Questa
▫️Vivado Simulator
▫️Verilator
💾 https://github.com/Kuree/pysv
#SV #systemverilog #python #simulation #cosimulation
@fpgasic
Supported Simulators
▫️Cadence Xcelium
▫️Synopsys VCS
▫️Mentor Questa
▫️Vivado Simulator
▫️Verilator
💾 https://github.com/Kuree/pysv
#SV #systemverilog #python #simulation #cosimulation
@fpgasic
OpenVAF - an innovative Verilog-A compiler for use in circuit simulator. The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A.
Features:
▫️fast compile times (usually below 1 second for most compact models)
▫️high-quality user interface
▫️easy setup
▫️fast simulations surpassing existing solutions by 30%-60%
OpenVAF currently contains the following useable projects:
1️⃣ VerilogAE allows obtaining model equations (calculates the value of a single Variable) from Verilog-A files
2️⃣ Melange is an experimental circuit simulator that leverage OpenVAF to gain access to compact models
Links:
📄 openvaf.semimod.de/
💾 github.com/pascalkuthe/OpenVAF
#simulation #model #veriloga
@fpgasic
Features:
▫️fast compile times (usually below 1 second for most compact models)
▫️high-quality user interface
▫️easy setup
▫️fast simulations surpassing existing solutions by 30%-60%
OpenVAF currently contains the following useable projects:
1️⃣ VerilogAE allows obtaining model equations (calculates the value of a single Variable) from Verilog-A files
2️⃣ Melange is an experimental circuit simulator that leverage OpenVAF to gain access to compact models
Links:
📄 openvaf.semimod.de/
💾 github.com/pascalkuthe/OpenVAF
#simulation #model #veriloga
@fpgasic
A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues.
This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity.
Links:
📄 https://arxiv.org/abs/2411.14299
💾 https://github.com/jitendra-bhandari/Masala-CHAI
#LLM #LLM4EDA #analog #SPICE #EDA #simulation
@fpgasic
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues.
This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity.
Links:
📄 https://arxiv.org/abs/2411.14299
💾 https://github.com/jitendra-bhandari/Masala-CHAI
#LLM #LLM4EDA #analog #SPICE #EDA #simulation
@fpgasic