OpenVAF - an innovative Verilog-A compiler for use in circuit simulator. The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A.

Features:
▫️fast compile times (usually below 1 second for most compact models)
▫️high-quality user interface
▫️easy setup
▫️fast simulations surpassing existing solutions by 30%-60%

OpenVAF currently contains the following useable projects:
1️⃣ VerilogAE allows obtaining model equations (calculates the value of a single Variable) from Verilog-A files
2️⃣ Melange is an experimental circuit simulator that leverage OpenVAF to gain access to compact models

Links:
📄 openvaf.semimod.de/
💾 github.com/pascalkuthe/OpenVAF

#simulation #model #veriloga
@fpgasic

Ramulator - a Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies, and various academic proposals.

Ramulator supports a wide array of commercial DRAM standards:
▫️DDR3, DDR4
▫️LPDDR3, LPDDR4
▫️GDDR5
▫️WIO, WIO2
▫️HBM
▫️SALP
▫️TL-DRAM
▫️RowClone
▫️DSARP

Links:
📄 http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
💾 https://github.com/CMU-SAFARI/ramulator

#ram #model #dram #ddr #hbm
@fpgasic

Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques).

Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3

Links:
📄 https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
💾 https://github.com/CMU-SAFARI/ramulator2

#ram #model #dram #ddr #hbm
@fpgasic