Ramulator - a Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies, and various academic proposals.

Ramulator supports a wide array of commercial DRAM standards:
▫️DDR3, DDR4
▫️LPDDR3, LPDDR4
▫️GDDR5
▫️WIO, WIO2
▫️HBM
▫️SALP
▫️TL-DRAM
▫️RowClone
▫️DSARP

Links:
📄 http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
💾 https://github.com/CMU-SAFARI/ramulator

#ram #model #dram #ddr #hbm
@fpgasic

Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques).

Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3

Links:
📄 https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
💾 https://github.com/CMU-SAFARI/ramulator2

#ram #model #dram #ddr #hbm
@fpgasic

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

In terms of benchmarking memory, it can be done better on FPGA, rather than on CPU/GPU. When benchmarking memory on an FPGA, the benchmarking hardware engine can directly attach to the memory such that there is no noise between the targeted memory and the benchmarking engine.

With Shuhai, before implementing the concrete application that contains a particular memory access pattern on the FPGA, we are able to benchmark the corresponding memory access pattern to make sure that the memory side will not be the bottleneck.

Links:
📄 https://ieeexplore.ieee.org/document/9114755
💾 https://github.com/RC4ML/Shuhai

#memory #ddr #hbm #benchmark
@fpgasic