elf2hex - converts ELF files to HEX files that are suitable for Verilog's readmemh.

Verilog test harnesses can't directly read ELF binaries but are instead required to be provided with a hexidecimal dump of a particular width and depth. This project allows users to easily create these files.

./elf2hex [-h] --bit-width BIT_WIDTH --input IN.ELF [--output OUT.HEX]

◦ https://github.com/sifive/elf2hex

#ELF #HEX #memory #init #verilog

Great guide about building multiport Memories on FPGA

#guide #multiport #memory #ram #blockram
@fpgasic

OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

💾 https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic

CACTI is an integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. By integrating all these models together, users can have confidence that tradeoffs between time, power, and area are all based on the same assumptions and, hence, are mutually consistent. CACTI is intended for use by computer architects to better understand the performance tradeoffs inherent in memory system organizations.

Power, delay, area, and cycle time model for
▫️ direct mapped caches
▫️ set-associative caches
▫️ fully associative caches
▫️ Embedded DRAM memories
▫️ Commodity DRAM memories

💾 https://github.com/HewlettPackard/cacti
📄 https://hpl.hp.com/research/cacti/


#memory #cache #PPA #estimation
@fpgasic

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

In terms of benchmarking memory, it can be done better on FPGA, rather than on CPU/GPU. When benchmarking memory on an FPGA, the benchmarking hardware engine can directly attach to the memory such that there is no noise between the targeted memory and the benchmarking engine.

With Shuhai, before implementing the concrete application that contains a particular memory access pattern on the FPGA, we are able to benchmark the corresponding memory access pattern to make sure that the memory side will not be the bottleneck.

Links:
📄 https://ieeexplore.ieee.org/document/9114755
💾 https://github.com/RC4ML/Shuhai

#memory #ddr #hbm #benchmark
@fpgasic