A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues.
This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity.
Links:
📄 https://arxiv.org/abs/2411.14299
💾 https://github.com/jitendra-bhandari/Masala-CHAI
#LLM #LLM4EDA #analog #SPICE #EDA #simulation
@fpgasic
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues.
This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity.
Links:
📄 https://arxiv.org/abs/2411.14299
💾 https://github.com/jitendra-bhandari/Masala-CHAI
#LLM #LLM4EDA #analog #SPICE #EDA #simulation
@fpgasic
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