VeriGen: A Large Language Model for Verilog Code Generation
The next step getting a Verilog fine-tuned LLM to generate the RTL; then we can kick-back & watch the whole SoC emerge autonomously. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.
💾 https://arxiv.org/abs/2308.00708
#verilog #sv #codegen #llm
@fpgasic
The next step getting a Verilog fine-tuned LLM to generate the RTL; then we can kick-back & watch the whole SoC emerge autonomously. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.
💾 https://arxiv.org/abs/2308.00708
#verilog #sv #codegen #llm
@fpgasic
A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues.
This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity.
Links:
📄 https://arxiv.org/abs/2411.14299
💾 https://github.com/jitendra-bhandari/Masala-CHAI
#LLM #LLM4EDA #analog #SPICE #EDA #simulation
@fpgasic
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues.
This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity.
Links:
📄 https://arxiv.org/abs/2411.14299
💾 https://github.com/jitendra-bhandari/Masala-CHAI
#LLM #LLM4EDA #analog #SPICE #EDA #simulation
@fpgasic