VeriGen: A Large Language Model for Verilog Code Generation
The next step getting a Verilog fine-tuned LLM to generate the RTL; then we can kick-back & watch the whole SoC emerge autonomously. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.
💾 https://arxiv.org/abs/2308.00708
#verilog #sv #codegen #llm
@fpgasic
The next step getting a Verilog fine-tuned LLM to generate the RTL; then we can kick-back & watch the whole SoC emerge autonomously. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.
💾 https://arxiv.org/abs/2308.00708
#verilog #sv #codegen #llm
@fpgasic