svlint - awesome SystemVerilog linter written in Rust
💾 https://github.com/dalance/svlint
📄 https://github.com/dpretet/dotfiles/blob/master/svlint.toml
#lint #linter #sv #systemverilog #rust
@fpgasic
💾 https://github.com/dalance/svlint
📄 https://github.com/dpretet/dotfiles/blob/master/svlint.toml
#lint #linter #sv #systemverilog #rust
@fpgasic
👍1
sv-parser - SystemVerilog parser library fully compliant with IEEE 1800-2017 written in Rust
💾 https://github.com/dalance/sv-parser
#parser #lexer #sv #systemverilog #rust
@fpgasic
💾 https://github.com/dalance/sv-parser
#parser #lexer #sv #systemverilog #rust
@fpgasic
👍3👏1
BENDER - a dependency management tool for hardware design projects written in Rust.
It provides a way to define dependencies among IPs, execute unit tests, and verify that the source files are valid input for various simulation and synthesis tools.
Principles
▫️Be as opt-in as possible
▫️Allow for reproducible builds
▫️Collect source files
▫️Manage dependencies
▫️Generate tool scripts
💾 https://github.com/pulp-platform/bender
📄 https://pulp-platform.org/docs/riscv_workshop_zurich/bender_wosh2019.pdf
#build #buildsystem #makefile #bender #ip #dependencies #scripts #rust
@fpgasic
It provides a way to define dependencies among IPs, execute unit tests, and verify that the source files are valid input for various simulation and synthesis tools.
Principles
▫️Be as opt-in as possible
▫️Allow for reproducible builds
▫️Collect source files
▫️Manage dependencies
▫️Generate tool scripts
💾 https://github.com/pulp-platform/bender
📄 https://pulp-platform.org/docs/riscv_workshop_zurich/bender_wosh2019.pdf
#build #buildsystem #makefile #bender #ip #dependencies #scripts #rust
@fpgasic
👍9🤩1
svinst - tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations (written in Rust).
💾 https://github.com/sgherbst/svinst
#parser #parsing #instantiation #sv #systemverilog #rust
@fpgasic
💾 https://github.com/sgherbst/svinst
#parser #parsing #instantiation #sv #systemverilog #rust
@fpgasic
👍4👏1