FPG𝔸SIC
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FPG/A/SIC tips and tricks

#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera

PS: also might be intresting @ipcores
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BENDER - a dependency management tool for hardware design projects written in Rust.

It provides a way to define dependencies among IPs, execute unit tests, and verify that the source files are valid input for various simulation and synthesis tools.

Principles
▫️Be as opt-in as possible
▫️Allow for reproducible builds
▫️Collect source files
▫️Manage dependencies
▫️Generate tool scripts

💾 https://github.com/pulp-platform/bender
📄 https://pulp-platform.org/docs/riscv_workshop_zurich/bender_wosh2019.pdf

#build #buildsystem #makefile #bender #ip #dependencies #scripts #rust
@fpgasic