Datasheet Scrubber - a utility that scrubs through large sets of PDF datasheets/documents in order to extract key circuit information. The information gathered is used to build a database of commercial off-the-shelf (COTS) IP that can be used to build larger SoC.

Datasheet Scrubber also define IP-XACT++, an extended version of IP-XACT, to encapsulate all the information needed for system generator, and port known IPs into the database. Doing this is really useful in finding the optimum SoC design based on user specifications.

Link:
◦ Description
◦ Sources

#datasheet #IPXACT #python #SoC #IP

Doulos is providing series of online training webinars including live interactive Q&A.

◦ April 3 - QEMU for Embedded System Developers
◦ April 8 - Integrating the Arm Cortex-M3 in a Xilinx FPGA
◦ April 15 - Getting Started with SystemVerilog
Functional Coverage
◦ April 17 - Why C is "The Language of Embedded"

For registration: https://www.doulos.com/content/training/webinars.php

#Doulos #onlinetraining #webinar #training #fpga #SV #digitaldesign #embeddedsystem #armcortex #xilinx

If you like Integrated Circuits, here is the NetFlix of IC Design: All past IEEE SSCS webinar videos & slides, ISSCC short courses & tutorials, and SSCSedu Lecture series are FREE (for a limited time), non-members can take advantage of this great offer.

FREE for a limited time: https://resourcecenter.sscs.ieee.org/

#webinar #onlinelearning #ieee #ic #sscs

Mentor's Functional Verification Training Series contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use SystemVerilog, HDL, UVM, CDC, ModelSim/Questa to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.

FREE for a 30-day access (hurry up to checkout until April 30): https://www.mentor.com/training/courses/functional-verification-training-library
Use promo code ODT-WECARE2020__30

PS: only corporate email are applicable

#Mentor #onlinetraining #webinar #training #verilog #SV #verification #FPGA

Yet Another VHDL tool performs parsing, semantic analysis, and elaboration. The goal is to at some point in the future integrate this with the yosys HDL synthesis tool.

Apparently, that's good starting point to develop your own VHDL parser.

https://github.com/rqou/yavhdl

#VHDL #parser #semantic #elaboration

Surelog tool providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench (System Verilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API).

Purpose: Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models (UHDM).

https://github.com/alainmarcel/Surelog

Also see similar proj: https://github.com/alainmarcel/Surelog#similar-projects

#SystemVerilog #parser #semantic #elaboration

VSCode-SystemVerilog - VS Code extension provides features to read, navigate and write SystemVerilog code much faster.

Features
◦ Syntax Highlighting
◦ Code snippets for many common blocks
◦ Instantiate module from already indexed module
◦ Linter capabilites with simulators
◦ Fast real-time error identification through an integrated SystemVerilog parser and IntelliSense (IEEE 1800-2017)

https://github.com/eirikpre/VSCode-SystemVerilog

#SystemVerilog #VSCode #editor

How to logging FPGA resource usage by commit to commit?

Here good try to create a tool to track tranding LUT/FF/Freq by every commit:
https://github.com/mattvenn/logLUTs

#git #commit #stats #python

elf2hex - converts ELF files to HEX files that are suitable for Verilog's readmemh.

Verilog test harnesses can't directly read ELF binaries but are instead required to be provided with a hexidecimal dump of a particular width and depth. This project allows users to easily create these files.

./elf2hex [-h] --bit-width BIT_WIDTH --input IN.ELF [--output OUT.HEX]

◦ https://github.com/sifive/elf2hex

#ELF #HEX #memory #init #verilog

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII - this capability will be released in the coming weeks with completed SoC design examples that have been sent to SkyWater for fabricaiton.

https://github.com/efabless/openlane

#GDSII #PDK #RTL #OpenROAD #Yosys #Magic #Netgen #SkyWater

Cadence online training FREE!
Get your first peek at the new system and your new possibilities

https://www.cadence.com/content/cadence-www/global/en_US/home/multimedia.html/content/dam/cadence-www/global/en_US/videos/training/cadence-learning-support.mp4

#Cadence #onlinetraining #webinar #training #ASIC #EDA

Great guide about building multiport Memories on FPGA

#guide #multiport #memory #ram #blockram
@fpgasic

Types and evolution of Xilinx's FPGA transceivers

#SerDes #GTP #GTX #GTH #GTY #GTZ #GTM
@fpgasic

svlint - SystemVerilog linter a tool that providing some static checks (with rule based system).

▫️Source
▫️Rule plugin

#HDL #checker #LINT #verilog #SV #rust
@fpgasic

Vim plugin to work easier with Verilog & SystemVerilog

https://github.com/dpretet/vim-veritoolbox

#vim #vi #verilog #SV #python
@fpgasic

BTW, you can find a huge collection of RTL sources on this channel.

Feel free to join and share!
t.me/ipcores

Verilog Template for VS Code Remote Development

Verilog template which is easy to develop, using VS Code Remote Development. It uses Icarus Verilog, GTKWave, and Docker.

https://github.com/ha2zakura/verilog-template

#VScode #MS #verilog #SV #docker #icarus #gtkwave
@fpgasic

Intel PSG is providing series of online training.
Due to COVID-19 these training is FREE!
It's live (nor recorded) training with instructors.
Get your advanced skills and your new possibilities!

https://www.intel.com/content/www/us/en/programmable/support/training/schedule.html

#Intel #onlinetraining #webinar #training #FPGA #Quartus #STA #HLS #OneAPI #PlatformDesigner

PyVCD - package writes Value Change Dump (VCD) files as specified in IEEE 1364-2005.
This tool also can generate GTKWave save files.

▫️ doc
▫️ src

#python #VCD #dump #GTKWave

HDElk - a web-based HDL diagramming tool. It was designed to permit the easy visual representation of Verilog or VHDL (generically HDL’s, Hardware Description Languages) in web pages by creation of simple javascript specification objects.

Links:
▫️ Doc
▫️ Src

#HDL #documentation #javascript #js #diagram #authoring