e.g. FPGA tool performance profiling to analyze FPGA performance (MHz, resources, runtime, etc)

https://github.com/SymbiFlow/fpga-tool-perf

#FPGA #profiling

Alterrnative of datasheets for lazy designers in CLI

Just find required P/N:

get_parts [-regexp] [-filter <arg>] <patterns>

And getting some pieces of info related to P/N:

report_property [get_parts <parts>]

#xilinx #FPGA #vivado #datasheet #tcl

Presentation: Introduction to ASIC design for FPGA developers

#doc #ASIC #FPGA #beginner

Quick & dirty approach to detect/prevent any attempt to JTAG access. The output signal might will use an almost infinite number of possible options, such as:

◦ Reset the internal MMCM/PLLs
◦ Gate off any internal clocks
◦ Drive the GSR or GTS inputs on the STARTUPEx primitive

#FPGA #Xilinx #JTAG #TamperDetection #protection #security

Automated flow for compressing convolution neural networks for efficient edge-computation with FPGA
#FPGA #NN #ML #CNN #YOLO #LeapMind #TensorFlow

LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
#FPGA #NN #ML #LegUp #LLVM #DNN #Python #XLA #TensorFlow

CLaaS - Custom Logic as a Service.
This solution, it significantly reduces the complexity of developing a hardware-accelerated application, bringing the platform within the reach of everyone, including startups, open-source enthusiasts and makers. With the framework, you can stream data directly between your custom FPGA kernel and application using standard websockets.

https://github.com/alessandrocomodi/fpga-webserver

#CLaaS #FPGA #web #framework #WebSocket #AWS

Doulos is providing series of online training webinars including live interactive Q&A.

◦ April 3 - QEMU for Embedded System Developers
◦ April 8 - Integrating the Arm Cortex-M3 in a Xilinx FPGA
◦ April 15 - Getting Started with SystemVerilog
Functional Coverage
◦ April 17 - Why C is "The Language of Embedded"

For registration: https://www.doulos.com/content/training/webinars.php

#Doulos #onlinetraining #webinar #training #fpga #SV #digitaldesign #embeddedsystem #armcortex #xilinx

Mentor's Functional Verification Training Series contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use SystemVerilog, HDL, UVM, CDC, ModelSim/Questa to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.

FREE for a 30-day access (hurry up to checkout until April 30): https://www.mentor.com/training/courses/functional-verification-training-library
Use promo code ODT-WECARE2020__30

PS: only corporate email are applicable

#Mentor #onlinetraining #webinar #training #verilog #SV #verification #FPGA

BTW, you can find a huge collection of RTL sources on this channel.

Feel free to join and share!
t.me/ipcores

Intel PSG is providing series of online training.
Due to COVID-19 these training is FREE!
It's live (nor recorded) training with instructors.
Get your advanced skills and your new possibilities!

https://www.intel.com/content/www/us/en/programmable/support/training/schedule.html

#Intel #onlinetraining #webinar #training #FPGA #Quartus #STA #HLS #OneAPI #PlatformDesigner

fp2p - FPGA Port To Pin tool.

Utility for safe and reusable port to pin assignment in multi-board FPGA designs.

The implementation has two main goals, safety (check as many potential human mistakes as possible) and reusability (reuse connections mappings, defined in files, in multiple designs). It is fully declarative and programming language-agnostic from the users perspective.

https://github.com/m-kru/fp2p

#FPGA #pinout #pin #multiboard #python
@fpgasic

PipelineC - a C-like hardware description language (HDL) adding HLS(high level synthesis)-like automatic pipelining as a language construct/compiler feature.

💾 https://github.com/JulianKemmerer/PipelineC

#HLS #C #VHDL #python #pipelines #FPGA
@fpgasic

Scripts for archiving legacy Altera software

n 2020, Intel published Customer Advisories ADV2011 and ADV2030 which formally discontinued MAX+PLUS II entirely and Quartus II versions released prior to 2014. Downloads of these software were removed from Intel's FPGA download center. By researching the various download infrastructures used by Altera over time, some versions were discovered to still be available if you knew where to look. This repository provides scripts and cached versions of metadata used to discover these versions and enable bulk download of them.

💾 https://github.com/kc8apf/altera_archiving

#Altera #FPGA #Quartus #Legacy
@fpgasic

Silice - A language for hardcoding Algorithms into FPGA hardware

It provides a thin abstraction above Verilog (a typical hardware description language), simplifying design without loosing precise control over the hardware. It gives the (optional) ability to write parts of your design as sequences of operations, subroutines that can be called, and to use control flow statements such as while and break. At the same time, Silice lets you fully exploit the parallelism of FPGA architectures, describing operations and algorithms that run in parallel and are precisely in sync.

💾 https://github.com/sylefeb/Silice

#FPGA #HLS #language
@fpgasic

Open-Source RISC-V GPGPU Project

Researchers have found a way to enable CUDA software toolkit support on a RISC-V GPGPU project called Vortex. The Vortex RISC-V GPGPU aims to provide a full-system RISC-V GPU based on RV32IMF ISA. That means 32-bit cores that can be scaled from 1-core to 32-core GPU designs. It supports OpenCL 1.2 graphics API, and today it got support for some CUDA action as well.

💾 https://t.me/ipcores/91
📄 https://www.tomshardware.com/news/risc-v-runs-cuda

#RISCV #GPGPU #GPU #FPGA #CUDA #Nvidia
@fpgasic

Rosetta - Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

It contains six fully-developed applications from machine learning and image/video processing domains, where each benchmark consists multiple compute kernels that expose diverse sources of parallelism.

These applications are developed under realistic design constraints, and are optimized at both kernel-level and application-level with the advanced features of HLS tools to meet these constraints.

💾 Code
📄 Paper


#hls #fpga #benchmark
@fpgasic