Two approaches to getting device-DNA from FPGA using Vivado:
1. GUI based solution
2. TCL based solution

https://www.xilinx.com/support/answers/64178.html

AR#64178 #DNA #TCL

Following command retrieves
the TEMPERATURE property from connected FPGA:
get_property TEMPERATURE [get_hw_sysmons]
To report all properties of HW_SYSMON use this in TCL console: report_property -all [lindex [get_hw_sysmons] 0]
#SysMon #TCL #XADC #Xilinx #Telemetry

Optionally run optimization if there are timing violations after placement

if {[ get_property SLACK [ get_timing_paths -max_paths 1 -nworst 1 -setup ] ] < 0 } {
    puts "INFO :: Found setup timing violations. Running physical optimization once."
    phys_opt_design -directive AggressiveExplore
    phys_opt_design -directive AlternateReplication
    phys_opt_design -directive AggressiveFanoutOpt
}

#Xilinx #Vivado #phys_opt_design #TCL #automation #slack #violation

Good example to start using design automation scripts to program bitstream into Xilinx FPGAs on Vivado CLI

https://github.com/lnls-dig/fpga-programming

#Xilinx #Vivado #CLI #TCL #JTAG @fpgasic

Alterrnative of datasheets for lazy designers in CLI

Just find required P/N:

get_parts [-regexp] [-filter <arg>] <patterns>

And getting some pieces of info related to P/N:

report_property [get_parts <parts>]

#xilinx #FPGA #vivado #datasheet #tcl

diearea - a script for analyzing and graphical representation of area occupied by some part of hierarhical design in Synopsys DC (based on dc_shell report parsing).

https://github.com/dmitrodem/sizefs

#ASIC #DC #tcl #area #report #sizefs #json

OpenSTA - the engine for gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints and print timing reports.

Sources, Docs

#TCL #STA #sdc #sdf #spef #timing #analyze #netlist

The OpenROAD team also has several amazing projects, e.g.:

◦ RePlAce - RePlAce global placement tool
◦ FastRoute4-lefdef - LEF/DEF/Rsyn-based router
◦ OpenDP - Open Source Detailed Placement engine
◦ TritonCTS - Srcs and calibration scripts for clock tree synthesis
◦ magic - OpenROAD specific Magic VLSI Layout Tool
◦ ioPlacer - IO and Pin Placer for Floorplan-Placement Subflow

#ASIC #TCL