Bitstream Interpretation Library (BIL) for reading and interpreting bitstream files targeted at Xilinx FPGA:

- Configuration raw data extraction from bitstream files
- XDL design regeneration out of configuration raw data
- Automated configuration mapping analyzation of a device

https://github.com/florianbenz/bil
#Xilinx #bitstream #BIL #XDL #XDLRC #RAW

Optionally run optimization if there are timing violations after placement

if {[ get_property SLACK [ get_timing_paths -max_paths 1 -nworst 1 -setup ] ] < 0 } {
    puts "INFO :: Found setup timing violations. Running physical optimization once."
    phys_opt_design -directive AggressiveExplore
    phys_opt_design -directive AlternateReplication
    phys_opt_design -directive AggressiveFanoutOpt
}

#Xilinx #Vivado #phys_opt_design #TCL #automation #slack #violation

Automation of Vivado installation on Windows using PowerShell

https://gist.github.com/steelcowboy/4897883fb25082248d64b2f64c782d0d

#Xilinx #Vivado #PowerShell #Windows #Automation @fpgasic

A demo to write to BRAM from File and read from BRAM to file for JTAG2AXI IP Core

https://gist.github.com/imrickysu/a30afc117ac7397fdff6

#Xilinx #Vivado #BRAM #JTAG2AXI @fpgasic

To get eFuse DNA Device ID from Xilinx FPGA:
vivado -mode batch -source get_dna.tcl

https://gist.github.com/kylemanna/d177fd0d562f23d419553689252ceab7

#Xilinx #Vivado #DNA #DeviceID @fpgasic

Good example to start using design automation scripts to program bitstream into Xilinx FPGAs on Vivado CLI

https://github.com/lnls-dig/fpga-programming

#Xilinx #Vivado #CLI #TCL #JTAG @fpgasic

SymbiFlow is a work-in-progress FOSS Verilog-to-Bitstream (end-to-end) FPGA synthesis flow, currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs. Think of it as the GCC of FPGAs.

https://symbiflow.github.io/
https://github.com/SymbiFlow

#xilinx #yosys #ice40 #series7 #latticesemi

By default Vivado Lab setup JTAG clock speed at 15MHz. You can improve bitstream downloading time twice with help of this command:

set_property PARAM.FREQUENCY 30000000 [get_hw_targets]

preceding to doing open_hw_target.

The 30MHz is maximal frequency for MSSPE interface of FT2232H IC which used in Xilinx/Digilent USB-to-JTAG adapters.

#Xilinx #JTAG #FT2232H #Digilent #bitstream

Knowledge base related to Xilinx SoC products contributed by Xilinx staff. Most info useful for SW engineer who use Xilinx SoC:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview

#Xilinx #MicroBlaze #ZYNQ #Linux #SoC #MPSoC

Alterrnative of datasheets for lazy designers in CLI

Just find required P/N:

get_parts [-regexp] [-filter <arg>] <patterns>

And getting some pieces of info related to P/N:

report_property [get_parts <parts>]

#xilinx #FPGA #vivado #datasheet #tcl

Vivado 2019.1 is available now

Download, WhatsNew, Videos

#Xilinx #Vivado #HLS

Quick & dirty approach to detect/prevent any attempt to JTAG access. The output signal might will use an almost infinite number of possible options, such as:

◦ Reset the internal MMCM/PLLs
◦ Gate off any internal clocks
◦ Drive the GSR or GTS inputs on the STARTUPEx primitive

#FPGA #Xilinx #JTAG #TamperDetection #protection #security

Xilinx Vitis slides from today's presentation:

Bring Your Applications to Life with Vitis

#Xilinx #Vitis #HLS #FaaS #AI #Alveo #SDAccel #SDSoC

#VitisAI has been released today at the #xdf2019 and is available for download now.

In a nutshell: it is the tool that takes your trained #tensorflow or #caffe model and optimises it for your #Xilinx hardware.
Or very simply spoken: the turbocharge for #versal-devices and their AI engines.

Xilinx DMA PCIe tutorial by Roy Messinger

#Xilinx #Vivado #DMA #PCIE #BAR #PIPE #XDMA #AXI #driver

Xilt - Command Line Tools for Xilinx Toolchain. Xilt assumes Xilinx ISE WebPack 14.7 is installed and only works on 64-bit Linux systems (this is a deliberate design decision since the ISE isn't officially supported on current versions of Windows).

Xilt can be used to:
◦ Build VHDL, Verilog and mixed mode FPGA projects.
◦ Runs xst, ngdbuild, map, par and bitgen all from one command invocation
◦ Filters output to show errors and warnings while suppressing all other messages
◦ Launch common Xilinx GUI tools (ISE, CoreGen and License Manager) without having to explicitly setup ISE environment paths
◦ Build places all intermediate files into a separate folder to keep your source folders clean

Usage example:

xilt build --device:xc6slx9-2-tqg144 myproj.vhd myproj.ucf

Link:
◦ Package
◦ Sources

#Xilinx #ISE #nodeJS #linux

Doulos is providing series of online training webinars including live interactive Q&A.

◦ April 3 - QEMU for Embedded System Developers
◦ April 8 - Integrating the Arm Cortex-M3 in a Xilinx FPGA
◦ April 15 - Getting Started with SystemVerilog
Functional Coverage
◦ April 17 - Why C is "The Language of Embedded"

For registration: https://www.doulos.com/content/training/webinars.php

#Doulos #onlinetraining #webinar #training #fpga #SV #digitaldesign #embeddedsystem #armcortex #xilinx

BTW, you can find a huge collection of RTL sources on this channel.

Feel free to join and share!
t.me/ipcores

Vivado 2021.2 is available now

💾 Download (be careful! 72GB 😱)
📄 What's New Vivado
📄 What's New Vitis

#Xilinx #Vivado #Vitis #HLS
@fpgasic

Did you know that Xilinx FPGA have Dynamically Reconfigurable Look-Up Table (LUT)?
It's called CFGLUT5

Note: This component occupies one of the eight LUT6 components within a CLBM.

#UG974 #Xilinx #recongif