Reusable Integration Framework for FPGA Accelerators (RIFFA) is a simple framework for communicating data from a host CPU to a FPGA via a PCI-E. RIFFA supports Windows/Linux, Altera/Xilinx, with bindings for C/C++, Python, MATLAB and Java.
https://github.com/KastnerRG/riffa
#PCI-E #DMA #Linux
https://github.com/KastnerRG/riffa
#PCI-E #DMA #Linux
GitHub
GitHub - KastnerRG/riffa: The RIFFA development repository
The RIFFA development repository. Contribute to KastnerRG/riffa development by creating an account on GitHub.
Knowledge base related to Xilinx SoC products contributed by Xilinx staff. Most info useful for SW engineer who use Xilinx SoC:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview
#Xilinx #MicroBlaze #ZYNQ #Linux #SoC #MPSoC
https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview
#Xilinx #MicroBlaze #ZYNQ #Linux #SoC #MPSoC
Xilt - Command Line Tools for Xilinx Toolchain. Xilt assumes Xilinx ISE WebPack 14.7 is installed and only works on 64-bit Linux systems (this is a deliberate design decision since the ISE isn't officially supported on current versions of Windows).
Xilt can be used to:
⦠Build VHDL, Verilog and mixed mode FPGA projects.
⦠Runs xst, ngdbuild, map, par and bitgen all from one command invocation
⦠Filters output to show errors and warnings while suppressing all other messages
⦠Launch common Xilinx GUI tools (ISE, CoreGen and License Manager) without having to explicitly setup ISE environment paths
⦠Build places all intermediate files into a separate folder to keep your source folders clean
Usage example:
⦠Package
⦠Sources
#Xilinx #ISE #nodeJS #linux
Xilt can be used to:
⦠Build VHDL, Verilog and mixed mode FPGA projects.
⦠Runs xst, ngdbuild, map, par and bitgen all from one command invocation
⦠Filters output to show errors and warnings while suppressing all other messages
⦠Launch common Xilinx GUI tools (ISE, CoreGen and License Manager) without having to explicitly setup ISE environment paths
⦠Build places all intermediate files into a separate folder to keep your source folders clean
Usage example:
xilt build --device:xc6slx9-2-tqg144 myproj.vhd myproj.ucfLink:
⦠Package
⦠Sources
#Xilinx #ISE #nodeJS #linux