FPGš”øSIC
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FPG/A/SIC tips and tricks

#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera

PS: also might be intresting @ipcores
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Quick & dirty approach to detect/prevent any attempt to JTAG access. The output signal might will use an almost infinite number of possible options, such as:

ā—¦ Reset the internal MMCM/PLLs
ā—¦ Gate off any internal clocks
ā—¦ Drive the GSR or GTS inputs on the STARTUPEx primitive

#FPGA #Xilinx #JTAG #TamperDetection #protection #security