FPGš”øSIC
2.13K subscribers
86 photos
12 files
89 links
FPG/A/SIC tips and tricks

#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera

PS: also might be intresting @ipcores
Download Telegram
Optionally run optimization if there are timing violations after placement

if {[ get_property SLACK [ get_timing_paths -max_paths 1 -nworst 1 -setup ] ] < 0 } {
puts "INFO :: Found setup timing violations. Running physical optimization once."
phys_opt_design -directive AggressiveExplore
phys_opt_design -directive AlternateReplication
phys_opt_design -directive AggressiveFanoutOpt
}


#Xilinx #Vivado #phys_opt_design #TCL #automation #slack #violation
ā¤1