PyMTL - an open-source python-based unified framework for multi-level hardware modeling and vertically integrated computer architecture research.

PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment for functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) modeling. PyMTL leverages the Python programming language to create a highly productive domain-specific embedded language for concurrent-structural modeling and hardware design.

A custom JIT engine automatically generates optimized C++ for CL and RTL models. To reduce the performance impact of the remaining unspecialized code, Sim JIT combines with an off-the-shelf Python interpreter with a meta-tracing JIT compiler (PyPy). Sim JIT+PyPy provides speedups of up to 72× for CL models and 200× for RTL models.

◦ Paper
◦ Tutorial + Examples
◦ Sources

#PyMTL #JIT #framework #python #modeling #verilator

Did you know that Icarus Verilog includes a non-standard random number generator as a built-in?

$mti_random()
$mti_dist_uniform

These functions are similar to the IEEE1364 standard $random functions, but they use the Mersenne Twister (MT19937) algorithm. This is considered an excellent random number generator, but does not generate the same sequence as the standardized $random.

#iverilog #simulation #verilog #random #RNG

BD_SHELL - is like a UNIX command line shell, but for manually writing and reading FPGA|ASIC registers on a 32bit Local Bus. Supports scripting of course and dumping register contents to a file. It works alongside SUMP2 as a diagnostic tool for chip bringup and debugging.

Fully cross platform compatible and much easier to maintain. BD_SHELL is part of "Backdoor" suite of tools for FPG/A/SIC diagnostics over a simple 2-pin FTDI cable for 1 Mbps UART communications using the Mesa Bus Protocol. The bd_server.py TCP server supports other links such a PCIe, SERDES, whatever you have that Python can talk to, bd_server.py can adapt to.

https://github.com/blackmesalabs/bd_shell

#debug #backdoor #FTDI #python #powershell

Quick & dirty approach to detect/prevent any attempt to JTAG access. The output signal might will use an almost infinite number of possible options, such as:

◦ Reset the internal MMCM/PLLs
◦ Gate off any internal clocks
◦ Drive the GSR or GTS inputs on the STARTUPEx primitive

#FPGA #Xilinx #JTAG #TamperDetection #protection #security

VHD2VL - free and opensource translator for synthesizable VHDL into Verilog 1995/2001. It does not support the full VHDL grammar - most of the testbench related features have been left out. Syntax and semantics are not carefully checked. vhd2vl assumes that the input is error-free.
Vhd2vl is written using lex (actually Flex), yacc (actually Bison), and C.

The most important VHDL constructs missing from this version are
◦ packages
◦ structures
◦ functions
◦ strings
◦ attributes

Project page + sources

#VHDL #Verilog #converter #translator #flex #bison

Automated flow for compressing convolution neural networks for efficient edge-computation with FPGA
#FPGA #NN #ML #CNN #YOLO #LeapMind #TensorFlow

LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
#FPGA #NN #ML #LegUp #LLVM #DNN #Python #XLA #TensorFlow

CLaaS - Custom Logic as a Service.
This solution, it significantly reduces the complexity of developing a hardware-accelerated application, bringing the platform within the reach of everyone, including startups, open-source enthusiasts and makers. With the framework, you can stream data directly between your custom FPGA kernel and application using standard websockets.

https://github.com/alessandrocomodi/fpga-webserver

#CLaaS #FPGA #web #framework #WebSocket #AWS

OpenSTA - the engine for gate level static timing verifier. As a stand-alone executable it can be used to verify the timing of a design using standard file formats. OpenSTA uses a TCL command interpreter to read the design, specify timing constraints and print timing reports.

Sources, Docs

#TCL #STA #sdc #sdf #spef #timing #analyze #netlist

The OpenROAD team also has several amazing projects, e.g.:

◦ RePlAce - RePlAce global placement tool
◦ FastRoute4-lefdef - LEF/DEF/Rsyn-based router
◦ OpenDP - Open Source Detailed Placement engine
◦ TritonCTS - Srcs and calibration scripts for clock tree synthesis
◦ magic - OpenROAD specific Magic VLSI Layout Tool
◦ ioPlacer - IO and Pin Placer for Floorplan-Placement Subflow

#ASIC #TCL

Xilinx Vitis slides from today's presentation:

Bring Your Applications to Life with Vitis

#Xilinx #Vitis #HLS #FaaS #AI #Alveo #SDAccel #SDSoC

#VitisAI has been released today at the #xdf2019 and is available for download now.

In a nutshell: it is the tool that takes your trained #tensorflow or #caffe model and optimises it for your #Xilinx hardware.
Or very simply spoken: the turbocharge for #versal-devices and their AI engines.

HDL Checker - a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer library VHDL files likely belong to, besides working out mixed language dependencies, compilation order, interpreting some compilers messages and providing some static checks.

https://github.com/suoto/hdl_checker

#HDL #checker #LINT #verilog #VHDL #SV #python

Xilinx DMA PCIe tutorial by Roy Messinger

#Xilinx #Vivado #DMA #PCIE #BAR #PIPE #XDMA #AXI #driver

RgGen - a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Features:
◦ Generate source files related to CSR from register map specifications
◦ SystemVerilog RTL
◦ UVM RAL model
◦ Register map documents written in Markdown
◦ Register map specifications can be written in human readable format:
◦ Ruby with APIs to describe register map information
◦ YAML
◦ JSON
◦ Spreadsheet (XLSX, XLS, OSD, CSV)

https://github.com/rggen/rggen

#CSR #Automation #tool #ruby #wiki #UVM #RegisterMap

vcd2wavedrom - a python script to transform a VCD file to wavedrom format. The tool have flexible config in json format.

vcd2wavedrom in fact is tb2svg tool that improve performance of prepare documentation.

https://github.com/Toroid-io/vcd2wavedrom

#vcd #wavedrom #waveform #testbench #waves #documentation

Xilt - Command Line Tools for Xilinx Toolchain. Xilt assumes Xilinx ISE WebPack 14.7 is installed and only works on 64-bit Linux systems (this is a deliberate design decision since the ISE isn't officially supported on current versions of Windows).

Xilt can be used to:
◦ Build VHDL, Verilog and mixed mode FPGA projects.
◦ Runs xst, ngdbuild, map, par and bitgen all from one command invocation
◦ Filters output to show errors and warnings while suppressing all other messages
◦ Launch common Xilinx GUI tools (ISE, CoreGen and License Manager) without having to explicitly setup ISE environment paths
◦ Build places all intermediate files into a separate folder to keep your source folders clean

Usage example:

xilt build --device:xc6slx9-2-tqg144 myproj.vhd myproj.ucf

Link:
◦ Package
◦ Sources

#Xilinx #ISE #nodeJS #linux