Yet Another VHDL tool performs parsing, semantic analysis, and elaboration. The goal is to at some point in the future integrate this with the yosys HDL synthesis tool.

Apparently, that's good starting point to develop your own VHDL parser.

https://github.com/rqou/yavhdl

#VHDL #parser #semantic #elaboration

Surelog tool providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench (System Verilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API).

Purpose: Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models (UHDM).

https://github.com/alainmarcel/Surelog

Also see similar proj: https://github.com/alainmarcel/Surelog#similar-projects

#SystemVerilog #parser #semantic #elaboration