Good example to start using design automation scripts to program bitstream into Xilinx FPGAs on Vivado CLI

https://github.com/lnls-dig/fpga-programming

#Xilinx #Vivado #CLI #TCL #JTAG @fpgasic

SymbiFlow is a work-in-progress FOSS Verilog-to-Bitstream (end-to-end) FPGA synthesis flow, currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs. Think of it as the GCC of FPGAs.

https://symbiflow.github.io/
https://github.com/SymbiFlow

#xilinx #yosys #ice40 #series7 #latticesemi

e.g. FPGA tool performance profiling to analyze FPGA performance (MHz, resources, runtime, etc)

https://github.com/SymbiFlow/fpga-tool-perf

#FPGA #profiling

Digilent Vivado Scripts contains a set of scripts for creating, maintaining, and releasing git repositories containing minimally version-controlled Vivado and Xilinx SDK projects. These scripts have been tested with Vivado 2018.2.

https://github.com/Digilent/digilent-vivado-scripts

#vivado #git #versioning

My Vivado .gitignore still uncomplete but might be useful (mostly for non-project mode):
https://gist.github.com/iDoka/6147ea6cf320f09d7ca39477b090486a

PS: Feel free to feedback in coments on github
#vivado #git #gitignore #versioning

Another approach offer Xilinx in AR#61232; they just exclude from "ignore list" (in .gitignore ) filetypes which sould be under version control:
https://www.xilinx.com/support/answers/61232.html

Additional reading:
https://www.xilinx.com/support/documentation/application_notes/xapp1165.pdf

#vivado #git #gitignore #versioning #XAPP1165 #UG1198

By default Vivado Lab setup JTAG clock speed at 15MHz. You can improve bitstream downloading time twice with help of this command:

set_property PARAM.FREQUENCY 30000000 [get_hw_targets]

preceding to doing open_hw_target.

The 30MHz is maximal frequency for MSSPE interface of FT2232H IC which used in Xilinx/Digilent USB-to-JTAG adapters.

#Xilinx #JTAG #FT2232H #Digilent #bitstream

In case of creating HDL-code in #SublimeText you can integrate simple linter like #Verilator (Free and OpenSource tool):

https://github.com/poucotm/SublimeLinter-contrib-verilator

#lint #verilog #SV

For other RTL-editors you can run #Verilator (as Linter) directly from CLI (customize command args with adding your secret sauce):

verilator --error-limit 100 \
    --default-language 1800-2012 \
    --bbox-sys --bbox-unsup -Wall \
    -Wno-DECLFILENAME \
    -Wno-IGNINC -Wno-IGNDEF \
    -Wno-WIDTH -Wno-STMTDLY \
    -Wno-UNDRIVEN \
    -Wno-PINCONNECTEMPTY \
    -Wno-INPUTPINEMPTY \
    -Wno-OUTPUTPINEMPTY

#lint #verilog #SV

Implements the Verilog Language Extension for Visual Studio Editor versions 2015, 2017, and 2019.

Download & Sources

#verilog #VisualStudio #SyntaxHiglighter

Experimental High Level Synthesis (HLS) from prototype based object oriented scripting language (Karuta) to RTL (Verilog) which might become useful for FPGA development. Project designed its own language Karuta just only for RTL design instead of reusing existing languages.
>800 commits

Some of following features are incorporated in the language constructs to make it easy to use:

∙ Prototype based object system to model design structures
∙ Flexible data types
◦ Integer with width. Custom operators for defined data types like FP16
∙ Communication primitives
◦ Threads, mailboxes, channels and so on
◦ AXI, RPC like handshake, GPIO, embedded verilog and so on
∙ HDL generators and optimizers
◦ Generates Verilog or HTML
◦ SSA based optimizers
◦ Scheduling and allocation based on device parameters

https://github.com/nlsynth/karuta

#HLS #Karuta #iroha #verilog

Knowledge base related to Xilinx SoC products contributed by Xilinx staff. Most info useful for SW engineer who use Xilinx SoC:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview

#Xilinx #MicroBlaze #ZYNQ #Linux #SoC #MPSoC

New book related to MPSoCs. Buy from Amazon or download the FREE e-book and build your knowledge of Zynq UltraScale+

https://www.zynq-mpsoc-book.com

#MPSoCs #ZYNQ #ML #PYNQ

Several videos about HBM vs GDDR6:

● HBM vs GDDR6: look at two different memory options, and the pros and cons of each
● GDDR6–HBM2 Tradeoffs: What type of DRAM works best where
● Latency Under Load: HBM2 vs GDDR6

#HBM2 #GDDR6 #DRAM #latency #tradeoff

Alterrnative of datasheets for lazy designers in CLI

Just find required P/N:

get_parts [-regexp] [-filter <arg>] <patterns>

And getting some pieces of info related to P/N:

report_property [get_parts <parts>]

#xilinx #FPGA #vivado #datasheet #tcl

Vivado 2019.1 is available now

Download, WhatsNew, Videos

#Xilinx #Vivado #HLS

Presentation: Introduction to ASIC design for FPGA developers

#doc #ASIC #FPGA #beginner

Wave Computing and Imperas introduce new MIPS Open Simulator MIPSOpenOVPsim - is a MIPS system architecture simulator, available at no cost, which implements a complete single-core CPU. MIPSOpenOVPsim is an entry ramp for software development, SoC testing and verification.

MIPSOpenOVPsim offers:
● A jump-start to software and firmware development during the SoC design cycle
● Early-stage implementation testing and Design Verification (DV) of MIPS CPU core designs
● Acceleration of compliance testing by providing a reference environment

MIPSOpenOVPsim helps SoC developers by providing a comprehensive testing platform for all MIPS Open specifications and extensions including:
● The MIPS 32 and 64-bit ISA Rev6 licensed under MIPS Open
● MIPS SIMD Extensions v1.0
● MIPS DSP Extensions
● MIPS Multi-Threading (MT)
● MIPS MCU
● microMIPS Architecture
● MIPS Virtualization (VZ)

Further details and download are available.

#MIPS #MIPSOpen #simulator #verification

Formal Verification with SymbiYosys and Yosys-SMTBMC
◦ Presentation Slides
◦ Examples

Investigating and Verifying Hardware Designs with Formal Open Source Tools
◦ Presentation Slides
◦ Examples

References:
==========

Yosys family:
◦ Yosys - a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains
◦ SymbiYosys - a front-end driver program for Yosys-based formal hardware verification flows

SAT and SMT solvers:
◦ Z3 Theorem Prover
◦ Yices2 SMT Solver
◦ Boolector
◦ ABC
◦ super_prove
◦ Avy

#Formal #Verification #SymbiYosys #Yosys #solver #publication #opensource

A padring generator for ASIC.
Tool makes padrings for ASICs using a LEF file and a placement/configuration file. The padrings can be output in GDS2, DEF and/or SVG format.

https://github.com/YosysHQ/padring

#ASIC #phydesign #padring #LEF #GDSII #DEF