Great guide about building multiport Memories on FPGA

#guide #multiport #memory #ram #blockram
@fpgasic

Types and evolution of Xilinx's FPGA transceivers

#SerDes #GTP #GTX #GTH #GTY #GTZ #GTM
@fpgasic

svlint - SystemVerilog linter a tool that providing some static checks (with rule based system).

▫️Source
▫️Rule plugin

#HDL #checker #LINT #verilog #SV #rust
@fpgasic

Vim plugin to work easier with Verilog & SystemVerilog

https://github.com/dpretet/vim-veritoolbox

#vim #vi #verilog #SV #python
@fpgasic

BTW, you can find a huge collection of RTL sources on this channel.

Feel free to join and share!
t.me/ipcores

Verilog Template for VS Code Remote Development

Verilog template which is easy to develop, using VS Code Remote Development. It uses Icarus Verilog, GTKWave, and Docker.

https://github.com/ha2zakura/verilog-template

#VScode #MS #verilog #SV #docker #icarus #gtkwave
@fpgasic

Intel PSG is providing series of online training.
Due to COVID-19 these training is FREE!
It's live (nor recorded) training with instructors.
Get your advanced skills and your new possibilities!

https://www.intel.com/content/www/us/en/programmable/support/training/schedule.html

#Intel #onlinetraining #webinar #training #FPGA #Quartus #STA #HLS #OneAPI #PlatformDesigner

PyVCD - package writes Value Change Dump (VCD) files as specified in IEEE 1364-2005.
This tool also can generate GTKWave save files.

▫️ doc
▫️ src

#python #VCD #dump #GTKWave

HDElk - a web-based HDL diagramming tool. It was designed to permit the easy visual representation of Verilog or VHDL (generically HDL’s, Hardware Description Languages) in web pages by creation of simple javascript specification objects.

Links:
▫️ Doc
▫️ Src

#HDL #documentation #javascript #js #diagram #authoring

[WiP] ligeia - replacement for GTKWave, written in Rust with high-performance and larger-than-memory traces in mind.

https://github.com/lachlansneff/ligeia

#rust #VCD #dump #GTKWave
@fpgasic

🛠 IEEE P1735 decryptor for VHDL

This tool allow to recover full source code of encrypted module (provided you have an extracted private key from the software you're using). Usually software vendors do not care much about hiding their private keys. The decryption is done in two stages:

1️⃣ using the private key, a session key is decrypted using RSA decryption procedure
2️⃣ data block is decoded using this session key and AES-128-CBC decryption procedure

💾 https://github.com/dmitrodem/p1735_decryptor

#decryptor #python #IP #VHDL #P1735 #encryption #protection #Aldec
@fpgasic

fp2p - FPGA Port To Pin tool.

Utility for safe and reusable port to pin assignment in multi-board FPGA designs.

The implementation has two main goals, safety (check as many potential human mistakes as possible) and reusability (reuse connections mappings, defined in files, in multiple designs). It is fully declarative and programming language-agnostic from the users perspective.

https://github.com/m-kru/fp2p

#FPGA #pinout #pin #multiboard #python
@fpgasic

Verilog-HDL/SystemVerilog/Bluespec support for VS Code

Features
▫️ Syntax Highlighting
◦ Verilog
◦ SystemVerilog
◦ Bluespec SystemVerilog
◦ Vivado UCF constraints
◦ Synopsys Design Constraints
▫️Simple Snippets
▫️Linting support from:
◦ Icarus Verilog
◦ Vivado Simulation
◦ Modelsim
◦ Verilator
▫️Ctags Integration
◦ Autocomplete
◦ Document Symbols Outline
◦ Hover over variable declaration
◦ Go to Definition & Peek Definition
◦ Module Instantiation

https://github.com/mshr-h/vscode-verilog-hdl-support

#VScode #MS #verilog #SV #bluespec #lint snippets #syntax #icarus #modelsim #verilator
@fpgasic

Dockerize Synopsys/Cadence EDA tools - is the Dockerfiles to dockerize popular EDA tools.

With docker images we could do:

▫️Build/test your design on the cloud server
▫️Maintain tools with as many different version as you want without issues
▫️Provide tools for you or your peer's desktop computer regardless of which kind of Linux you are using
▫️Continuous Integration (CI)

💾 https://github.com/limerainne/Dockerize-EDA

#docker #cadence #synopsys #eda
@fpgasic

OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

💾 https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic

pysv - a lightweight Python library that allows functional models to be written in Python and then executed inside standard SystemVerilog simulators, via DPI.

Supported Simulators
▫️Cadence Xcelium
▫️Synopsys VCS
▫️Mentor Questa
▫️Vivado Simulator
▫️Verilator


💾 https://github.com/Kuree/pysv

#SV #systemverilog #python #simulation #cosimulation
@fpgasic

PipelineC - a C-like hardware description language (HDL) adding HLS(high level synthesis)-like automatic pipelining as a language construct/compiler feature.

💾 https://github.com/JulianKemmerer/PipelineC

#HLS #C #VHDL #python #pipelines #FPGA
@fpgasic

asciiwave - WaveDrom to ASCII art

💾 https://github.com/Wren6991/asciiwave

#waves #diagram #python #asciiart #wavedrom
@fpgasic

CACTI is an integrated cache and memory access time, cycle time, area, leakage, and dynamic power model. By integrating all these models together, users can have confidence that tradeoffs between time, power, and area are all based on the same assumptions and, hence, are mutually consistent. CACTI is intended for use by computer architects to better understand the performance tradeoffs inherent in memory system organizations.

Power, delay, area, and cycle time model for
▫️ direct mapped caches
▫️ set-associative caches
▫️ fully associative caches
▫️ Embedded DRAM memories
▫️ Commodity DRAM memories

💾 https://github.com/HewlettPackard/cacti
📄 https://hpl.hp.com/research/cacti/


#memory #cache #PPA #estimation
@fpgasic

Scripts for archiving legacy Altera software

n 2020, Intel published Customer Advisories ADV2011 and ADV2030 which formally discontinued MAX+PLUS II entirely and Quartus II versions released prior to 2014. Downloads of these software were removed from Intel's FPGA download center. By researching the various download infrastructures used by Altera over time, some versions were discovered to still be available if you knew where to look. This repository provides scripts and cached versions of metadata used to discover these versions and enable bulk download of them.

💾 https://github.com/kc8apf/altera_archiving

#Altera #FPGA #Quartus #Legacy
@fpgasic