Surelog tool providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench (System Verilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API).

Purpose: Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models (UHDM).

https://github.com/alainmarcel/Surelog

Also see similar proj: https://github.com/alainmarcel/Surelog#similar-projects

#SystemVerilog #parser #semantic #elaboration

VSCode-SystemVerilog - VS Code extension provides features to read, navigate and write SystemVerilog code much faster.

Features
◦ Syntax Highlighting
◦ Code snippets for many common blocks
◦ Instantiate module from already indexed module
◦ Linter capabilites with simulators
◦ Fast real-time error identification through an integrated SystemVerilog parser and IntelliSense (IEEE 1800-2017)

https://github.com/eirikpre/VSCode-SystemVerilog

#SystemVerilog #VSCode #editor

How to logging FPGA resource usage by commit to commit?

Here good try to create a tool to track tranding LUT/FF/Freq by every commit:
https://github.com/mattvenn/logLUTs

#git #commit #stats #python

elf2hex - converts ELF files to HEX files that are suitable for Verilog's readmemh.

Verilog test harnesses can't directly read ELF binaries but are instead required to be provided with a hexidecimal dump of a particular width and depth. This project allows users to easily create these files.

./elf2hex [-h] --bit-width BIT_WIDTH --input IN.ELF [--output OUT.HEX]

◦ https://github.com/sifive/elf2hex

#ELF #HEX #memory #init #verilog

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII - this capability will be released in the coming weeks with completed SoC design examples that have been sent to SkyWater for fabricaiton.

https://github.com/efabless/openlane

#GDSII #PDK #RTL #OpenROAD #Yosys #Magic #Netgen #SkyWater

Cadence online training FREE!
Get your first peek at the new system and your new possibilities

https://www.cadence.com/content/cadence-www/global/en_US/home/multimedia.html/content/dam/cadence-www/global/en_US/videos/training/cadence-learning-support.mp4

#Cadence #onlinetraining #webinar #training #ASIC #EDA

Great guide about building multiport Memories on FPGA

#guide #multiport #memory #ram #blockram
@fpgasic

Types and evolution of Xilinx's FPGA transceivers

#SerDes #GTP #GTX #GTH #GTY #GTZ #GTM
@fpgasic

svlint - SystemVerilog linter a tool that providing some static checks (with rule based system).

▫️Source
▫️Rule plugin

#HDL #checker #LINT #verilog #SV #rust
@fpgasic

Vim plugin to work easier with Verilog & SystemVerilog

https://github.com/dpretet/vim-veritoolbox

#vim #vi #verilog #SV #python
@fpgasic

BTW, you can find a huge collection of RTL sources on this channel.

Feel free to join and share!
t.me/ipcores

Verilog Template for VS Code Remote Development

Verilog template which is easy to develop, using VS Code Remote Development. It uses Icarus Verilog, GTKWave, and Docker.

https://github.com/ha2zakura/verilog-template

#VScode #MS #verilog #SV #docker #icarus #gtkwave
@fpgasic

Intel PSG is providing series of online training.
Due to COVID-19 these training is FREE!
It's live (nor recorded) training with instructors.
Get your advanced skills and your new possibilities!

https://www.intel.com/content/www/us/en/programmable/support/training/schedule.html

#Intel #onlinetraining #webinar #training #FPGA #Quartus #STA #HLS #OneAPI #PlatformDesigner

PyVCD - package writes Value Change Dump (VCD) files as specified in IEEE 1364-2005.
This tool also can generate GTKWave save files.

▫️ doc
▫️ src

#python #VCD #dump #GTKWave

HDElk - a web-based HDL diagramming tool. It was designed to permit the easy visual representation of Verilog or VHDL (generically HDL’s, Hardware Description Languages) in web pages by creation of simple javascript specification objects.

Links:
▫️ Doc
▫️ Src

#HDL #documentation #javascript #js #diagram #authoring

[WiP] ligeia - replacement for GTKWave, written in Rust with high-performance and larger-than-memory traces in mind.

https://github.com/lachlansneff/ligeia

#rust #VCD #dump #GTKWave
@fpgasic

🛠 IEEE P1735 decryptor for VHDL

This tool allow to recover full source code of encrypted module (provided you have an extracted private key from the software you're using). Usually software vendors do not care much about hiding their private keys. The decryption is done in two stages:

1️⃣ using the private key, a session key is decrypted using RSA decryption procedure
2️⃣ data block is decoded using this session key and AES-128-CBC decryption procedure

💾 https://github.com/dmitrodem/p1735_decryptor

#decryptor #python #IP #VHDL #P1735 #encryption #protection #Aldec
@fpgasic

fp2p - FPGA Port To Pin tool.

Utility for safe and reusable port to pin assignment in multi-board FPGA designs.

The implementation has two main goals, safety (check as many potential human mistakes as possible) and reusability (reuse connections mappings, defined in files, in multiple designs). It is fully declarative and programming language-agnostic from the users perspective.

https://github.com/m-kru/fp2p

#FPGA #pinout #pin #multiboard #python
@fpgasic

Verilog-HDL/SystemVerilog/Bluespec support for VS Code

Features
▫️ Syntax Highlighting
◦ Verilog
◦ SystemVerilog
◦ Bluespec SystemVerilog
◦ Vivado UCF constraints
◦ Synopsys Design Constraints
▫️Simple Snippets
▫️Linting support from:
◦ Icarus Verilog
◦ Vivado Simulation
◦ Modelsim
◦ Verilator
▫️Ctags Integration
◦ Autocomplete
◦ Document Symbols Outline
◦ Hover over variable declaration
◦ Go to Definition & Peek Definition
◦ Module Instantiation

https://github.com/mshr-h/vscode-verilog-hdl-support

#VScode #MS #verilog #SV #bluespec #lint snippets #syntax #icarus #modelsim #verilator
@fpgasic

Dockerize Synopsys/Cadence EDA tools - is the Dockerfiles to dockerize popular EDA tools.

With docker images we could do:

▫️Build/test your design on the cloud server
▫️Maintain tools with as many different version as you want without issues
▫️Provide tools for you or your peer's desktop computer regardless of which kind of Linux you are using
▫️Continuous Integration (CI)

💾 https://github.com/limerainne/Dockerize-EDA

#docker #cadence #synopsys #eda
@fpgasic