Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques).
Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3
Links:
📄 https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
💾 https://github.com/CMU-SAFARI/ramulator2
#ram #model #dram #ddr #hbm
@fpgasic
Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3
Links:
📄 https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
💾 https://github.com/CMU-SAFARI/ramulator2
#ram #model #dram #ddr #hbm
@fpgasic
CompressedLUT - a tool for lossless compression of lookup tables and generation of their hardware files in Verilog and C++ for RTL and HLS designs.
Links:
📄 https://doi.org/10.1145/3626202.3637575
💾 https://github.com/kiabuzz/CompressedLUT
#acceleration #LUT #lookuptable #lossless #compression #table-size-reduction #table-based-function-implementation
@fpgasic
Links:
📄 https://doi.org/10.1145/3626202.3637575
💾 https://github.com/kiabuzz/CompressedLUT
#acceleration #LUT #lookuptable #lossless #compression #table-size-reduction #table-based-function-implementation
@fpgasic
Forwarded from VLSI HUB (Dmitry Murzinov)
DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs
https://pulp-platform.org/docs/riscvmunich2024/RISCV_europe_summit_2024_DUTCTL_poster.pdf
@vlsihub
https://pulp-platform.org/docs/riscvmunich2024/RISCV_europe_summit_2024_DUTCTL_poster.pdf
@vlsihub
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FloorSet: The First Million-Scale Dataset for SoC Design Planning.
FloorSet is aimed at advancing machine learning for floorplanning physical layouts of systems-on-a-chip (SoCs) and its sub-systems. It features 2 million synthetic benchmark circuits that capture real design constraints and objectives, all carefully sampled from actual design distributions.
FloorSet addresses key challenges of training-data availability and reproducibility in the chip-design world, driving fundamental research in large-scale constrained optimization problems.
Links:
📄 https://arxiv.org/abs/2405.05480
💾 https://github.com/IntelLabs/FloorSet
#floorplan #SoC #MLaimed #CAE #opensource
@fpgasic
FloorSet is aimed at advancing machine learning for floorplanning physical layouts of systems-on-a-chip (SoCs) and its sub-systems. It features 2 million synthetic benchmark circuits that capture real design constraints and objectives, all carefully sampled from actual design distributions.
FloorSet addresses key challenges of training-data availability and reproducibility in the chip-design world, driving fundamental research in large-scale constrained optimization problems.
Links:
📄 https://arxiv.org/abs/2405.05480
💾 https://github.com/IntelLabs/FloorSet
#floorplan #SoC #MLaimed #CAE #opensource
@fpgasic
Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA
In terms of benchmarking memory, it can be done better on FPGA, rather than on CPU/GPU. When benchmarking memory on an FPGA, the benchmarking hardware engine can directly attach to the memory such that there is no noise between the targeted memory and the benchmarking engine.
With Shuhai, before implementing the concrete application that contains a particular memory access pattern on the FPGA, we are able to benchmark the corresponding memory access pattern to make sure that the memory side will not be the bottleneck.
Links:
📄 https://ieeexplore.ieee.org/document/9114755
💾 https://github.com/RC4ML/Shuhai
#memory #ddr #hbm #benchmark
@fpgasic
In terms of benchmarking memory, it can be done better on FPGA, rather than on CPU/GPU. When benchmarking memory on an FPGA, the benchmarking hardware engine can directly attach to the memory such that there is no noise between the targeted memory and the benchmarking engine.
With Shuhai, before implementing the concrete application that contains a particular memory access pattern on the FPGA, we are able to benchmark the corresponding memory access pattern to make sure that the memory side will not be the bottleneck.
Links:
📄 https://ieeexplore.ieee.org/document/9114755
💾 https://github.com/RC4ML/Shuhai
#memory #ddr #hbm #benchmark
@fpgasic
A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues.
This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity.
Links:
📄 https://arxiv.org/abs/2411.14299
💾 https://github.com/jitendra-bhandari/Masala-CHAI
#LLM #LLM4EDA #analog #SPICE #EDA #simulation
@fpgasic
Masala-CHAI is the first fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists.
Automating workflow could accelerate the creation of finetuned LLMs for analog circuit design and verification. We identify key challenges in this automation and evaluate the multi-modal capabilities of state-of-the-art LLMs, particularly GPT-4, to address these issues.
This approach aims to create an end-to-end SPICE netlist generator from circuit schematic images, tackling the long-standing hurdle of accurate netlist generation. Our framework demonstrates significant performance improvements, tested on approximately 2,100 schematics of varying complexity.
Links:
📄 https://arxiv.org/abs/2411.14299
💾 https://github.com/jitendra-bhandari/Masala-CHAI
#LLM #LLM4EDA #analog #SPICE #EDA #simulation
@fpgasic
Automated SV Assertion Interface Generator:
It generates a SV assertion interface for a given RTL design. It analyzes the RTL code to extract ports and registers, and creates an interface that can be used for writing assertions.
Features
▫️ Automatically detects the top-level module in the design hierarchy
▫️ Extracts ports and registers from the RTL code
▫️ Handles naming conflicts by using hierarchical paths
▫️ Generates a bind statement for easy integration
▫️ Creates well-formatted and organized interface code
▫️ Supports different modes for interface generation (SPY signals source):
◾️ Ports only (input | output | inout)
◾️ Registers only (signals with "_s" suffix)
◾️ Both ports and registers (default)
Links
💾 https://github.com/Inkub/SV-assertions-IF-generator
#SVA #SV #generator #checker
@fpgasic
It generates a SV assertion interface for a given RTL design. It analyzes the RTL code to extract ports and registers, and creates an interface that can be used for writing assertions.
Features
▫️ Automatically detects the top-level module in the design hierarchy
▫️ Extracts ports and registers from the RTL code
▫️ Handles naming conflicts by using hierarchical paths
▫️ Generates a bind statement for easy integration
▫️ Creates well-formatted and organized interface code
▫️ Supports different modes for interface generation (SPY signals source):
◾️ Ports only (input | output | inout)
◾️ Registers only (signals with "_s" suffix)
◾️ Both ports and registers (default)
Links
💾 https://github.com/Inkub/SV-assertions-IF-generator
#SVA #SV #generator #checker
@fpgasic