“Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers.

https://github.com/VLSI-EDA/PoC

#IP #primitives #library #VHDL

VHD2VL - free and opensource translator for synthesizable VHDL into Verilog 1995/2001. It does not support the full VHDL grammar - most of the testbench related features have been left out. Syntax and semantics are not carefully checked. vhd2vl assumes that the input is error-free.
Vhd2vl is written using lex (actually Flex), yacc (actually Bison), and C.

The most important VHDL constructs missing from this version are
◦ packages
◦ structures
◦ functions
◦ strings
◦ attributes

Project page + sources

#VHDL #Verilog #converter #translator #flex #bison

HDL Checker - a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer library VHDL files likely belong to, besides working out mixed language dependencies, compilation order, interpreting some compilers messages and providing some static checks.

https://github.com/suoto/hdl_checker

#HDL #checker #LINT #verilog #VHDL #SV #python

Yet Another VHDL tool performs parsing, semantic analysis, and elaboration. The goal is to at some point in the future integrate this with the yosys HDL synthesis tool.

Apparently, that's good starting point to develop your own VHDL parser.

https://github.com/rqou/yavhdl

#VHDL #parser #semantic #elaboration

BTW, you can find a huge collection of RTL sources on this channel.

Feel free to join and share!
t.me/ipcores

🛠 IEEE P1735 decryptor for VHDL

This tool allow to recover full source code of encrypted module (provided you have an extracted private key from the software you're using). Usually software vendors do not care much about hiding their private keys. The decryption is done in two stages:

1️⃣ using the private key, a session key is decrypted using RSA decryption procedure
2️⃣ data block is decoded using this session key and AES-128-CBC decryption procedure

💾 https://github.com/dmitrodem/p1735_decryptor

#decryptor #python #IP #VHDL #P1735 #encryption #protection #Aldec
@fpgasic

PipelineC - a C-like hardware description language (HDL) adding HLS(high level synthesis)-like automatic pipelining as a language construct/compiler feature.

💾 https://github.com/JulianKemmerer/PipelineC

#HLS #C #VHDL #python #pipelines #FPGA
@fpgasic

TerosHDL 2.0.0 has been released. You can install it from VSCode market.

Features:
▫️Support for VHDL, Verilog, System Verilog
▫️Windows, Linux, Mac
▫️Simulators and tools support: Vivado, ModelSim, GHDL, Verilator, Icarus, VCS, Yosys, VUnit, cocotb, Diamond, Icestorm, ISE, Quartus, Radiant, Spyglass, Symbiflow, Trellis, Xcelium...
▫️Go to definition
▫️Hover
▫️Hiterachy viewer
▫️Dependencies viewer
▫️Syntax highlighting
▫️Template generator
▫️Automatic documentation
▫️Command line documenter
▫️Verilog/SV schematic viewer
▫️Errors linter
▫️Style linter: Verible
▫️Code formatting
▫️State machine viewer
▫️State machine designer
▫️Code snippets and grammar

💾 https://marketplace.visualstudio.com/items?itemName=teros-technology.teroshdl
📄 https://terostechnology.github.io/terosHDLdoc/

#verilog #vhdl #systemverilog #teroshdl #vunit #edalize #wavedrom #vscode
@fpgasic

Versatile list of HDL lint tools

📄 https://airhdl.com/blog/2017/02/08/fpga-lint-tools/
(updated August 2022)

#lint #linter #sv #verilog #vhdl
@fpgasic