Surelog tool providing a complete System Verilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench (System Verilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API).

Purpose: Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models (UHDM).

https://github.com/alainmarcel/Surelog

Also see similar proj: https://github.com/alainmarcel/Surelog#similar-projects

#SystemVerilog #parser #semantic #elaboration

VSCode-SystemVerilog - VS Code extension provides features to read, navigate and write SystemVerilog code much faster.

Features
◦ Syntax Highlighting
◦ Code snippets for many common blocks
◦ Instantiate module from already indexed module
◦ Linter capabilites with simulators
◦ Fast real-time error identification through an integrated SystemVerilog parser and IntelliSense (IEEE 1800-2017)

https://github.com/eirikpre/VSCode-SystemVerilog

#SystemVerilog #VSCode #editor

pysv - a lightweight Python library that allows functional models to be written in Python and then executed inside standard SystemVerilog simulators, via DPI.

Supported Simulators
▫️Cadence Xcelium
▫️Synopsys VCS
▫️Mentor Questa
▫️Vivado Simulator
▫️Verilator


💾 https://github.com/Kuree/pysv

#SV #systemverilog #python #simulation #cosimulation
@fpgasic

TerosHDL 2.0.0 has been released. You can install it from VSCode market.

Features:
▫️Support for VHDL, Verilog, System Verilog
▫️Windows, Linux, Mac
▫️Simulators and tools support: Vivado, ModelSim, GHDL, Verilator, Icarus, VCS, Yosys, VUnit, cocotb, Diamond, Icestorm, ISE, Quartus, Radiant, Spyglass, Symbiflow, Trellis, Xcelium...
▫️Go to definition
▫️Hover
▫️Hiterachy viewer
▫️Dependencies viewer
▫️Syntax highlighting
▫️Template generator
▫️Automatic documentation
▫️Command line documenter
▫️Verilog/SV schematic viewer
▫️Errors linter
▫️Style linter: Verible
▫️Code formatting
▫️State machine viewer
▫️State machine designer
▫️Code snippets and grammar

💾 https://marketplace.visualstudio.com/items?itemName=teros-technology.teroshdl
📄 https://terostechnology.github.io/terosHDLdoc/

#verilog #vhdl #systemverilog #teroshdl #vunit #edalize #wavedrom #vscode
@fpgasic

svlint - awesome SystemVerilog linter written in Rust

💾 https://github.com/dalance/svlint
📄 https://github.com/dpretet/dotfiles/blob/master/svlint.toml

#lint #linter #sv #systemverilog #rust
@fpgasic

SVUnit - an open-source test framework for ASIC and FPGA developers writing Verilog and SystemVerilog code.

SVUnit is automated, fast, lightweight and easy to use making it the only SystemVerilog test framework in existence suited to both design and verification engineers that aspire to high quality code and low bug rates.

💾 https://github.com/svunit/svunit
📄 http://www.agilesoc.com/svunit

#test #testbench #verification #sv #systemverilog #svunit
@fpgasic

sv-parser - SystemVerilog parser library fully compliant with IEEE 1800-2017 written in Rust

💾 https://github.com/dalance/sv-parser

#parser #lexer #sv #systemverilog #rust
@fpgasic

svinst - tool takes a SystemVerilog file as input and produces as output the module(s) declared in that file, along with the module(s) instantiated in each one of those module declarations (written in Rust).

💾 https://github.com/sgherbst/svinst

#parser #parsing #instantiation #sv #systemverilog #rust
@fpgasic

Verilog and SystemVerilog cheatsheet

#verilog #systemverilog #cheatsheet #digitaldesign
@fpgasic