Presentation: Introduction to ASIC design for FPGA developers

#doc #ASIC #FPGA #beginner

A padring generator for ASIC.
Tool makes padrings for ASICs using a LEF file and a placement/configuration file. The padrings can be output in GDS2, DEF and/or SVG format.

https://github.com/YosysHQ/padring

#ASIC #phydesign #padring #LEF #GDSII #DEF

ASIC Pinout Drawer - a simple pin assignment generator for IC case.

Input:
◦ CSV or AsciiDoc table

Output:
◦ SVG or PNG drawing

https://github.com/iDoka/asic-pinout-drawer

#ASIC #techdoc #techwriting #datasheet #asciidoc #svg

diearea - a script for analyzing and graphical representation of area occupied by some part of hierarhical design in Synopsys DC (based on dc_shell report parsing).

https://github.com/dmitrodem/sizefs

#ASIC #DC #tcl #area #report #sizefs #json

The OpenROAD team also has several amazing projects, e.g.:

◦ RePlAce - RePlAce global placement tool
◦ FastRoute4-lefdef - LEF/DEF/Rsyn-based router
◦ OpenDP - Open Source Detailed Placement engine
◦ TritonCTS - Srcs and calibration scripts for clock tree synthesis
◦ magic - OpenROAD specific Magic VLSI Layout Tool
◦ ioPlacer - IO and Pin Placer for Floorplan-Placement Subflow

#ASIC #TCL

Cadence online training FREE!
Get your first peek at the new system and your new possibilities

https://www.cadence.com/content/cadence-www/global/en_US/home/multimedia.html/content/dam/cadence-www/global/en_US/videos/training/cadence-learning-support.mp4

#Cadence #onlinetraining #webinar #training #ASIC #EDA

BTW, you can find a huge collection of RTL sources on this channel.

Feel free to join and share!
t.me/ipcores

OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

💾 https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic

OpenTimer - a High-Performance Timing Analysis Tool for VLSI Systems.

OpenTimer is a new static timing analysis (STA) tool to help IC designers quickly verify the circuit timing. It is developed completely from the ground up using C++17 to efficiently support parallel and incremental timing.

Features:
▫️Industry standard format (.lib, .v, .spef, .sdc) support
▫️Graph- and path-based timing analysis
▫️Parallel incremental timing for fast timing closure
▫️Award-winning tools and golden timers in CAD Contests

💾 https://github.com/OpenTimer/OpenTimer

#vlsi #asic #sta #statictiminganalysis #circuitanalysis
@fpgasic

Logic - CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Features:
▫️Cross platform, cross IDE
▫️No need to create separate scripts for simulation and synthesis
▫️No need to create separate scripts for different tools (Quartus, Vivado, ModelSim, ...)
▫️Supports incremental compilation
▫️Supports parallel compilation
▫️Maintain the same file consistency between simulation and synthesis for different tools
▫️Share the same HDL source code base and IP cores for various FPGA projects
▫️Integration with CI and CD like Jenkins, Hudson, GitLab, etc.
▫️Run RTL unit tests under ctest: pass/fail, time execution, timeout, parallel execution, tests selection
▫️Run the same unit tests with different parameters
▫️Easy to integrate with other projects as git submodule
▫️Custom UVM printers: JSON
▫️Modern HDL testing library written in C++11 using UVM-SystemC
▫️Support for Clang 3.5+
▫️Support for GCC 4.9+

💾 https://github.com/tymonx/logic
📄 https://github.com/tymonx/logic/wiki

#vlsi #asic #build #automation #ci #cd
@fpgasic