Optionally run optimization if there are timing violations after placement

if {[ get_property SLACK [ get_timing_paths -max_paths 1 -nworst 1 -setup ] ] < 0 } {
    puts "INFO :: Found setup timing violations. Running physical optimization once."
    phys_opt_design -directive AggressiveExplore
    phys_opt_design -directive AlternateReplication
    phys_opt_design -directive AggressiveFanoutOpt
}

#Xilinx #Vivado #phys_opt_design #TCL #automation #slack #violation

Automation of Vivado installation on Windows using PowerShell

https://gist.github.com/steelcowboy/4897883fb25082248d64b2f64c782d0d

#Xilinx #Vivado #PowerShell #Windows #Automation @fpgasic

RgGen - a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Features:
◦ Generate source files related to CSR from register map specifications
◦ SystemVerilog RTL
◦ UVM RAL model
◦ Register map documents written in Markdown
◦ Register map specifications can be written in human readable format:
◦ Ruby with APIs to describe register map information
◦ YAML
◦ JSON
◦ Spreadsheet (XLSX, XLS, OSD, CSV)

https://github.com/rggen/rggen

#CSR #Automation #tool #ruby #wiki #UVM #RegisterMap

Logic - CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Features:
▫️Cross platform, cross IDE
▫️No need to create separate scripts for simulation and synthesis
▫️No need to create separate scripts for different tools (Quartus, Vivado, ModelSim, ...)
▫️Supports incremental compilation
▫️Supports parallel compilation
▫️Maintain the same file consistency between simulation and synthesis for different tools
▫️Share the same HDL source code base and IP cores for various FPGA projects
▫️Integration with CI and CD like Jenkins, Hudson, GitLab, etc.
▫️Run RTL unit tests under ctest: pass/fail, time execution, timeout, parallel execution, tests selection
▫️Run the same unit tests with different parameters
▫️Easy to integrate with other projects as git submodule
▫️Custom UVM printers: JSON
▫️Modern HDL testing library written in C++11 using UVM-SystemC
▫️Support for Clang 3.5+
▫️Support for GCC 4.9+

💾 https://github.com/tymonx/logic
📄 https://github.com/tymonx/logic/wiki

#vlsi #asic #build #automation #ci #cd
@fpgasic