RgGen - a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.

Features:
◦ Generate source files related to CSR from register map specifications
◦ SystemVerilog RTL
◦ UVM RAL model
◦ Register map documents written in Markdown
◦ Register map specifications can be written in human readable format:
◦ Ruby with APIs to describe register map information
◦ YAML
◦ JSON
◦ Spreadsheet (XLSX, XLS, OSD, CSV)

https://github.com/rggen/rggen

#CSR #Automation #tool #ruby #wiki #UVM #RegisterMap