PyMTL - an open-source python-based unified framework for multi-level hardware modeling and vertically integrated computer architecture research.

PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment for functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) modeling. PyMTL leverages the Python programming language to create a highly productive domain-specific embedded language for concurrent-structural modeling and hardware design.

A custom JIT engine automatically generates optimized C++ for CL and RTL models. To reduce the performance impact of the remaining unspecialized code, Sim JIT combines with an off-the-shelf Python interpreter with a meta-tracing JIT compiler (PyPy). Sim JIT+PyPy provides speedups of up to 72× for CL models and 200× for RTL models.

◦ Paper
◦ Tutorial + Examples
◦ Sources

#PyMTL #JIT #framework #python #modeling #verilator

BD_SHELL - is like a UNIX command line shell, but for manually writing and reading FPGA|ASIC registers on a 32bit Local Bus. Supports scripting of course and dumping register contents to a file. It works alongside SUMP2 as a diagnostic tool for chip bringup and debugging.

Fully cross platform compatible and much easier to maintain. BD_SHELL is part of "Backdoor" suite of tools for FPG/A/SIC diagnostics over a simple 2-pin FTDI cable for 1 Mbps UART communications using the Mesa Bus Protocol. The bd_server.py TCP server supports other links such a PCIe, SERDES, whatever you have that Python can talk to, bd_server.py can adapt to.

https://github.com/blackmesalabs/bd_shell

#debug #backdoor #FTDI #python #powershell