Key differences between BlockRAM and UltraRAMwell.

#UG573 #Xilinx #BRAM #UltraRAM

Virtex Ultrascale+ VU13P dramatically boost DSP capacity (compare with VU9P)

Two approaches to getting device-DNA from FPGA using Vivado:
1. GUI based solution
2. TCL based solution

https://www.xilinx.com/support/answers/64178.html

AR#64178 #DNA #TCL

“Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers.

https://github.com/VLSI-EDA/PoC

#IP #primitives #library #VHDL

Latency-insensitive Environment for Application Programming (LEAP) is a set of modules that provide a convenient platform for the development of FPGA-based applications.

http://www.leap-fpga.org/

RTL, Cmodel, and testbench for NVIDIA Deep Learning Accelerator (NVDLA). It's a free and open architecture that promotes a standard way to design deep learning inference accelerators.

https://github.com/nvdla/hw

Did you know that now Intel chipsets Z390 and C246 supports up to 128GB RAM (4x 32GB DRR4 DIMM). It's open great opportunity for using desktop system as server for FPGA/ASIC design tasks.

https://www.gigabyte.com/Press/News/1669
#server #software #RAM #chipset

Good solution to replace direct instantiating vendor-dependent clock buffer BUFG like that:

BUFG bufg_inst (
  .I(clkin),
  .O(clk_pcie)
);

instread to use the HDL-pragma like that (verilog):

(* clock_buffer_type = "BUFG" *) input clk_pcie;

Another BUFx type also aplicable for this pragma

#Xilinx #BUFG #primitives

Simple example to use DNA for protection against cloning FPGA bitstream (device-locked approach)

info: http://www.markharvey.info/des/bitlock/bitlock.html
code: https://github.com/foolmarks/bitlock

#Xilinx #DNA #clone-protection

Xilinx Ultrascale/US+ Cheatsheet for PLL/MMCM settings #Xilinx #US #US+ #PLLE #MMCME

Simple example for family-independent approach. Just pass -verilog_define ULTRASCALE as option to synth_design cmd. Or don't pass.

Excellent example for create constraint in case of using standalone (and cascaded!) clock multiplexors in FPGA:
https://www.xilinx.com/support/answers/59484.html

#Xilinx #BUFGMUX #XDC #ClockMux

Good starting point how to work with dynamically tuned PLL/MMCM by DRP #XAPP888 #PLL #MMCM #Xilinx #PDF

Good starting point how to work with dynamically tuned PLL/MMCM by DRP #XAPP888 #PLL #MMCM #Xilinx #sources

Reusable Integration Framework for FPGA Accelerators (RIFFA) is a simple framework for communicating data from a host CPU to a FPGA via a PCI-E. RIFFA supports Windows/Linux, Altera/Xilinx, with bindings for C/C++, Python, MATLAB and Java.

https://github.com/KastnerRG/riffa
#PCI-E #DMA #Linux

One of my favorite part of UG949: RTL designer should know into which one primitives (and how many logic levels) infers strings of HDL

Open source tool for reading and writing Vivado design checkpoint (DCP) files. Its mission is to enable power users greater flexibility in customizing solutions http://www.rapidwright.io/ #DCP #Vivado

RapidWright: Enabling Custom Crafted Implementations for FPGAs #RapidWright #Vivado #DCP

Yet another solution (IP+driver) for DMA over PCI-E for Linux/Windows Xilinx/Altera. http://xillybus.com/ #DMA #PCI-E #RIFFA #Xillybus

Vivado Workflow for Generating Relocatable, Out-Of-Context End-User Configuration Tiles

https://github.com/bgottschall/reloc
#Xilinx #PR #OOC #tiles #PartialReconfiguration #PBlock #HierarhicalDesign #OutOfContext