āPile of Coresā provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers.
https://github.com/VLSI-EDA/PoC
#IP #primitives #library #VHDL
https://github.com/VLSI-EDA/PoC
#IP #primitives #library #VHDL
GitHub
GitHub - VLSI-EDA/PoC: IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Facultyā¦
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische UniversitƤt Dresden, Germany - VLSI-EDA/PoC
Good solution to replace direct instantiating vendor-dependent clock buffer BUFG like that:
#Xilinx #BUFG #primitives
BUFG bufg_inst (instread to use the HDL-pragma like that (verilog):
.I(clkin),
.O(clk_pcie)
);
(* clock_buffer_type = "BUFG" *) input clk_pcie;Another BUFx type also aplicable for this pragma
#Xilinx #BUFG #primitives