In case of creating HDL-code in #SublimeText you can integrate simple linter like #Verilator (Free and OpenSource tool):

https://github.com/poucotm/SublimeLinter-contrib-verilator

#lint #verilog #SV

For other RTL-editors you can run #Verilator (as Linter) directly from CLI (customize command args with adding your secret sauce):

verilator --error-limit 100 \
    --default-language 1800-2012 \
    --bbox-sys --bbox-unsup -Wall \
    -Wno-DECLFILENAME \
    -Wno-IGNINC -Wno-IGNDEF \
    -Wno-WIDTH -Wno-STMTDLY \
    -Wno-UNDRIVEN \
    -Wno-PINCONNECTEMPTY \
    -Wno-INPUTPINEMPTY \
    -Wno-OUTPUTPINEMPTY

#lint #verilog #SV

PyMTL - an open-source python-based unified framework for multi-level hardware modeling and vertically integrated computer architecture research.

PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment for functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) modeling. PyMTL leverages the Python programming language to create a highly productive domain-specific embedded language for concurrent-structural modeling and hardware design.

A custom JIT engine automatically generates optimized C++ for CL and RTL models. To reduce the performance impact of the remaining unspecialized code, Sim JIT combines with an off-the-shelf Python interpreter with a meta-tracing JIT compiler (PyPy). Sim JIT+PyPy provides speedups of up to 72× for CL models and 200× for RTL models.

◦ Paper
◦ Tutorial + Examples
◦ Sources

#PyMTL #JIT #framework #python #modeling #verilator

Verilog-HDL/SystemVerilog/Bluespec support for VS Code

Features
▫️ Syntax Highlighting
◦ Verilog
◦ SystemVerilog
◦ Bluespec SystemVerilog
◦ Vivado UCF constraints
◦ Synopsys Design Constraints
▫️Simple Snippets
▫️Linting support from:
◦ Icarus Verilog
◦ Vivado Simulation
◦ Modelsim
◦ Verilator
▫️Ctags Integration
◦ Autocomplete
◦ Document Symbols Outline
◦ Hover over variable declaration
◦ Go to Definition & Peek Definition
◦ Module Instantiation

https://github.com/mshr-h/vscode-verilog-hdl-support

#VScode #MS #verilog #SV #bluespec #lint snippets #syntax #icarus #modelsim #verilator
@fpgasic