FPGš”øSIC
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FPG/A/SIC tips and tricks

#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera

PS: also might be intresting @ipcores
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Digilent Vivado Scripts contains a set of scripts for creating, maintaining, and releasing git repositories containing minimally version-controlled Vivado and Xilinx SDK projects. These scripts have been tested with Vivado 2018.2.

https://github.com/Digilent/digilent-vivado-scripts

#vivado #git #versioning
My Vivado .gitignore still uncomplete but might be useful (mostly for non-project mode):
https://gist.github.com/iDoka/6147ea6cf320f09d7ca39477b090486a

PS: Feel free to feedback in coments on github
#vivado #git #gitignore #versioning
Another approach offer Xilinx in AR#61232; they just exclude from "ignore list" (in .gitignore ) filetypes which sould be under version control:
https://www.xilinx.com/support/answers/61232.html

Additional reading:
https://www.xilinx.com/support/documentation/application_notes/xapp1165.pdf

#vivado #git #gitignore #versioning #XAPP1165 #UG1198
How to logging FPGA resource usage by commit to commit?

Here good try to create a tool to track tranding LUT/FF/Freq by every commit:
https://github.com/mattvenn/logLUTs

#git #commit #stats #python