PonyLink - a bi-directional chip-to-chip interface that is using only a single signal wire between the two chips. Naturally this wire is used in a half-duplex fashion. For faster link speeds the use of a #LVDS pair is recommended. The cores are tested on #Xilinx Series 7 and #Lattice iCE40 FPGAs.

On the chip-facing side #PonyLink provides a transmit and receive #AXI Stream as well as 8 GPIO inputs and 8 GPIO outputs. PonyLink handles all the low-level tasks, including flow control and detection of failed transfers and automatic resend.

The main features of the core are that it only requires one single data line between the chips and that it can operate on resonable data rates (compared to the clock rates of the clocks driving the cores, usually over 0.5 MBit/s per MHz).

Features:
- typical net data rates of over 100 MBit/s at 166 MHz
- can utilize up to 4x serdes hardware for higher link speed
- support for any #AXIS TDATA and TUSER width and TLAST signal
- bi-directional communication over a single data line (usually LVDS)
- works without a dedicated hardware block for clock recovery
- dc-free signaling, allowing for caps or magnetics in the link
- embedded clock and control signals (using #8b10b encoding)

https://github.com/cliffordwolf/PonyLink
https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt
#verilog #python #protocol #serialinterface
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USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

Current solutions for USB3 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A) or external FIFO (FTDI FT60X or Cypress FX3). With this project, we want to see if it's possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip).

https://github.com/enjoy-digital/usb3_pipe

#USB3 #PIPE #PHY #verilog #LiteX #python #Xilinx #Lattice

Open Source USB test suite is an open source test suite for USB IP cores. It currently supports USB1.1 and will be extended for higher revisions in the future.

◦ https://github.com/antmicro/usb-test-suite-build - top level repo
◦ https://github.com/antmicro/usb-test-suite-cocotb-usb - cocotb_usb
◦ https://github.com/antmicro/usb-test-suite-testbenches - test and wrapper scripts

#verification #cocotb #python #USB #tb

A high performance streaming FFT core based on Bailey's 4-step large FFT algorithm (focused on speed optimizing: Fmax is up to 30% higher than Xilinx FFT IP)

Data input/output are continuous with no gaps between frames. Currently only supporting power-of-two sizes and fixed point data.

Top level VHDL code is generated by the script codegen/gen_fft.py.

https://github.com/owocomm-0/fpga-fft

#FFT #DSP #VHDL #generator #python #multicycle_path

parser-gen - Network packet parser generator. This generator produces synthesizable SystemVerilog.

It generates both fixed and programmable parsers. Fixed parsers use a parse graph that is chosen at generation time, while programmable parsers use a parse graph that is chosen at run time. The logic in a fixed parser is generated specifically for the chosen parse graph. The logic in a programmable parser is independent of the parse graph; however, the parse graph is used to build the testbench and to populate the parse state table (emulated TCAM/RAM) module.

Links:
▫️ Documentation
▫️ Sources

#python #perl #sv #SystemVerilog #network #verification #tcp #udp #stimulus #tb
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Verilog LFSR - Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation.

▫️lfsr.v - Parametrizable combinatorial LFSR/CRC module
▫️lfsr_crc.v - Parametrizable CRC computation wrapper
▫️lfsr_descramble.v - Parametrizable LFSR self-synchronizing descrambler
▫️lfsr_prbs_check.v - Parametrizable PRBS checker wrapper
▫️lfsr_prbs_gen.v - Parametrizable PRBS generator wrapper
▫️lfsr_scramble.v - Parametrizable LFSR self-synchronizing scrambler

Links:
▫️ Sources

#verilog #python #MyHDL #LFSR #CRC
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