HPC Guru (Twitter)
“It’s good to be lucky,” @AyarLabs CEO @Wuischpard
For Ayar Labs, the company best known for optical chip-to-chip interconnects, the industry-wide adoption of #chiplets couldn’t have come at a better time
https://www.eetimes.com/at-ayar-labs-its-all-coming-together/
#HPC #AI via @eetimes
“It’s good to be lucky,” @AyarLabs CEO @Wuischpard
For Ayar Labs, the company best known for optical chip-to-chip interconnects, the industry-wide adoption of #chiplets couldn’t have come at a better time
https://www.eetimes.com/at-ayar-labs-its-all-coming-together/
#HPC #AI via @eetimes
EE Times
At Ayar Labs, It’s All Coming Together - EE Times
An EE Times Exclusive interview with Ayar Labs CEO Charlie Wuischpard explores the future of optical chip-to-chip interconnects.
HPC Guru (Twitter)
.@Intel’s Road to a Universal #Quantum Computer Is Via #Chiplets
https://www.hpcwire.com/2022/10/11/intels-road-to-a-universal-quantum-computer-is-via-chiplets/
#QuantumComputing #HPC via @HPCwire
.@Intel’s Road to a Universal #Quantum Computer Is Via #Chiplets
https://www.hpcwire.com/2022/10/11/intels-road-to-a-universal-quantum-computer-is-via-chiplets/
#QuantumComputing #HPC via @HPCwire
HPCwire (Twitter)
@AMDServer’s fourth-generation Epyc, “Genoa,” can offer up to 96 5nm cores across 12 #Chiplets, a milestone referred to by AMD as, “a significant upgrade in core performance.”
http://ow.ly/zLiV50LJO8G #HPC
@AMDServer’s fourth-generation Epyc, “Genoa,” can offer up to 96 5nm cores across 12 #Chiplets, a milestone referred to by AMD as, “a significant upgrade in core performance.”
http://ow.ly/zLiV50LJO8G #HPC
HPCwire (Twitter)
Semiconductor Companies Create Building Block for Chiplet Design
http://ow.ly/yvXo50Mz481 #HPC #chiplets
Semiconductor Companies Create Building Block for Chiplet Design
http://ow.ly/yvXo50Mz481 #HPC #chiplets
HPCwire
Semiconductor Companies Create Building Block for Chiplet Design
Intel's CEO Pat Gelsinger last week made a grand proclamation that chips will be for the next few decades what oil and gas was to the world over the last 50 years. While that remains to be seen, two technology associations are joining hands to develop building…
HPCwire (Twitter)
Ayar Labs to Demo ‘Commercial-Grade’ 4Tbps #Optical I/O Solution
http://ow.ly/iOrl50N5Sct #HPC #photonics #chiplets #Ayar
Ayar Labs to Demo ‘Commercial-Grade’ 4Tbps #Optical I/O Solution
http://ow.ly/iOrl50N5Sct #HPC #photonics #chiplets #Ayar
HPCwire
Ayar Labs to Demo 'Commercial-Grade' 4Tbps Optical I/O Solution
Ayar Labs, founded in 2015, is pursuing optics as a means of driving higher interconnect speeds and efficiencies in computing. Now, the company is announcing that it plans to demonstrate […]
insideHPC.com (Twitter)
Fraunhofer IIS/EAS Selects Achronix Embedded FPGAs (eFPGAs) to Build Heterogeneous Chiplet Demonstrator for HPC
https://wp.me/p3RLHQ-nMO
@FraunhoferIIS @AchronixCorp #HPC #FPGA #chiplets
Fraunhofer IIS/EAS Selects Achronix Embedded FPGAs (eFPGAs) to Build Heterogeneous Chiplet Demonstrator for HPC
https://wp.me/p3RLHQ-nMO
@FraunhoferIIS @AchronixCorp #HPC #FPGA #chiplets
High-Performance Computing News Analysis | insideHPC
Fraunhofer IIS/EAS Selects Achronix Embedded FPGAs (eFPGAs) to Build Heterogeneous Chiplet Demonstrator for HPC
Santa Clara, Calif., and Dresden, Germany, April 25, 2023 – Fraunhofer IIS/EAS, an applied research institute in advanced package solution design, and [...]
HPCwire (Twitter)
For the First Time, UCIe Shares Bandwidth Speeds Between Chiplets
http://ow.ly/ZyCu50OI7rz #HPC #chiplets #UCIe #ISC
For the First Time, UCIe Shares Bandwidth Speeds Between Chiplets
http://ow.ly/ZyCu50OI7rz #HPC #chiplets #UCIe #ISC
HPCwire
For the First Time, UCIe Shares Bandwidth Speeds Between Chiplets
The first numbers of the available bandwidth between chiplets is out – UCIe is estimating that chiplet packages could squeeze out communication speeds of 630Gbps, or 0.63Tbps, in a very tight area. That number was shared by the Universal Chiplet Interconnect…
HPCwire (Twitter)
How AMD Used Its Chiplet Advantage to Design MI300X GPU and Bergamo CPU
https://ow.ly/TSbt50OOPMn #HPC #AI #AMD #chiplets
How AMD Used Its Chiplet Advantage to Design MI300X GPU and Bergamo CPU
https://ow.ly/TSbt50OOPMn #HPC #AI #AMD #chiplets
HPCwire
How AMD Used Its Chiplet Advantage to Design MI300X GPU and Bergamo CPU
Swap out a few silicon parts, and voila, you have a spanking new chip that did not take much work to design. That is how AMD's CEO, Lisa Su described the company making of its new MI300X GPU and its 128-core Epyc chip code-named Bergamo, which is targeted…
HPC Guru (Twitter)
RT @HPCwire: How AMD Used Its Chiplet Advantage to Design MI300X GPU and Bergamo CPU
https://ow.ly/TSbt50OOPMn #HPC #AI #AMD #chiplets
RT @HPCwire: How AMD Used Its Chiplet Advantage to Design MI300X GPU and Bergamo CPU
https://ow.ly/TSbt50OOPMn #HPC #AI #AMD #chiplets
HPCwire
How AMD Used Its Chiplet Advantage to Design MI300X GPU and Bergamo CPU
Swap out a few silicon parts, and voila, you have a spanking new chip that did not take much work to design. That is how AMD's CEO, Lisa Su described the company making of its new MI300X GPU and its 128-core Epyc chip code-named Bergamo, which is targeted…
HPCwire (Twitter)
The Universal Chiplet Interconnect Express revealed the first #bandwidth speed between #chiplets at #ISC2023. Learn about #chiplet packages and bandwidth here: https://t.co/6HnssWhrgP https://t.co/IDMvoGHa4I
The Universal Chiplet Interconnect Express revealed the first #bandwidth speed between #chiplets at #ISC2023. Learn about #chiplet packages and bandwidth here: https://t.co/6HnssWhrgP https://t.co/IDMvoGHa4I
HPCwire
For the First Time, UCIe Shares Bandwidth Speeds Between Chiplets
The first numbers of the available bandwidth between chiplets is out – UCIe is estimating that chiplet packages could squeeze out communication speeds of 630Gbps, or 0.63Tbps, in a very tight area. That number was shared by the Universal Chiplet Interconnect…
HPCwire (Twitter)
@NVIDIAAI plans to release #GPUs every year, according to its #roadmap. Learn about the road map and how #chiplets could define it. ow.ly/jhES50PXLkp
@NVIDIAAI plans to release #GPUs every year, according to its #roadmap. Learn about the road map and how #chiplets could define it. ow.ly/jhES50PXLkp
HPC Guru (Twitter)
Intel #18A is on track for production in 2025
Advanced packaging technologies (EMIB, Foveros Direct 3D) to meet the increasing demand for #chiplets in the #AI-driven era
Low yields *could* be a major issue
https://www.counterpointresearch.com/insights/rebooting-growth-intel-to-launch-18a-process-node-based-cpus-in-2025/
#HPC via @CounterPointTR
Intel #18A is on track for production in 2025
Advanced packaging technologies (EMIB, Foveros Direct 3D) to meet the increasing demand for #chiplets in the #AI-driven era
Low yields *could* be a major issue
https://www.counterpointresearch.com/insights/rebooting-growth-intel-to-launch-18a-process-node-based-cpus-in-2025/
#HPC via @CounterPointTR