FPGš”øSIC
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FPG/A/SIC tips and tricks

#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera

PS: also might be intresting @ipcores
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For other RTL-editors you can run #Verilator (as Linter) directly from CLI (customize command args with adding your secret sauce):

verilator --error-limit 100 \
--default-language 1800-2012 \
--bbox-sys --bbox-unsup -Wall \
-Wno-DECLFILENAME \
-Wno-IGNINC -Wno-IGNDEF \
-Wno-WIDTH -Wno-STMTDLY \
-Wno-UNDRIVEN \
-Wno-PINCONNECTEMPTY \
-Wno-INPUTPINEMPTY \
-Wno-OUTPUTPINEMPTY


#lint #verilog #SV