Latest Published Articles:
Hardware Architecture
#HardwareArchitecture
🗒 SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation
👥 Khaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song, Dmitry Evtyushkin, Dmitry Ponomarev, Nael Abu-Ghazaleh
📗 PDF
🗒 Development of FEB Configuration Test Board for ATLAS NSW Upgrade
👥 Houbing Lu, Feng Li, Peng Miao, Kun Hu, Zhilei Zhang, Rongqi Sun, Qingli Ma, Ge Jin
📗 PDF
🗒 VLSI Design Of Advanced Digital Filters
👥 Rozita Teymourzadeh
📗 PDF
🗒 Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis
👥 Rozita Teymourzadeh, Mometo Jim Abigo, Mok Vee Hoong
📗 PDF
🗒 Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique
👥 Yazan Samir Algnabi, Furat A. Aldaamee, Rozita Teymourzadeh
📗 PDF
🗒 Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor
👥 Rozita Teymourzadeh, Memtode Jim, Mok Vee hong
📗 PDF
🗒 FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure
👥 Yazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman, Md Shabiul Islam
📗 PDF
🗒 Mitigating Wordline Crosstalk using Adaptive Trees of Counters
👥 Seyed Mohammad Seyedzadeh, Alex K. Jones, Rami Melhem
📗 PDF
🗒 CMOS: Dynamic Multi-key Obfuscation Structure for Strong PUFs
👥 Jiliang Zhang, Lu Wan
📗 PDF
🗒 Gemini: Reducing DRAM Cache Hit Latency by Hybrid Mappings
👥 Ye Chi
📗 PDF
🗒 Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems
👥 Xiaoyuan Wang
📗 PDF
🗒 An Efficient Graph Accelerator with Parallel Data Conflict Management
👥 Pengcheng Yao
📗 PDF
🗒 A programmable clock generator for automatic Quality Assurance of LOCx2
👥 Zhi-yue Wang, Tian-kuan Liu, Qi-jie Tang, Yi Feng, Jian Wang
📗 PDF
🗒 LaKe: An Energy Efficient, Low Latency, Accelerated Key-Value Store
👥 Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
📗 PDF
🗒 Accelerating CNN inference on FPGAs: A Survey
👥 Kamel Abdelouahab, Maxime Pelcat, Jocelyn Serot, François Berry
📗 PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
🗒 SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation
👥 Khaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song, Dmitry Evtyushkin, Dmitry Ponomarev, Nael Abu-Ghazaleh
🗒 Development of FEB Configuration Test Board for ATLAS NSW Upgrade
👥 Houbing Lu, Feng Li, Peng Miao, Kun Hu, Zhilei Zhang, Rongqi Sun, Qingli Ma, Ge Jin
🗒 VLSI Design Of Advanced Digital Filters
👥 Rozita Teymourzadeh
🗒 Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis
👥 Rozita Teymourzadeh, Mometo Jim Abigo, Mok Vee Hoong
🗒 Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique
👥 Yazan Samir Algnabi, Furat A. Aldaamee, Rozita Teymourzadeh
🗒 Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor
👥 Rozita Teymourzadeh, Memtode Jim, Mok Vee hong
🗒 FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure
👥 Yazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman, Md Shabiul Islam
🗒 Mitigating Wordline Crosstalk using Adaptive Trees of Counters
👥 Seyed Mohammad Seyedzadeh, Alex K. Jones, Rami Melhem
🗒 CMOS: Dynamic Multi-key Obfuscation Structure for Strong PUFs
👥 Jiliang Zhang, Lu Wan
🗒 Gemini: Reducing DRAM Cache Hit Latency by Hybrid Mappings
👥 Ye Chi
🗒 Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems
👥 Xiaoyuan Wang
🗒 An Efficient Graph Accelerator with Parallel Data Conflict Management
👥 Pengcheng Yao
🗒 A programmable clock generator for automatic Quality Assurance of LOCx2
👥 Zhi-yue Wang, Tian-kuan Liu, Qi-jie Tang, Yi Feng, Jian Wang
🗒 LaKe: An Energy Efficient, Low Latency, Accelerated Key-Value Store
👥 Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
🗒 Accelerating CNN inference on FPGAs: A Survey
👥 Kamel Abdelouahab, Maxime Pelcat, Jocelyn Serot, François Berry
#HardwareArchitecture
AI Python & arXiv Channel
Latest Published Articles:
Hardware Architecture
#HardwareArchitecture
🗒 Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs
👥 Thomas B. Preußer
📗 PDF
🗒 LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels
👥 Julian Stecklina, Thomas Prescher
📗 PDF
🗒 A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB
👥 Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham
📗 PDF
🗒 RAPIDNN: In-Memory Deep Neural Network Acceleration Framework
👥 Mohsen Imani, Mohammad Samragh, Yeseong Kim, Saransh Gupta, Farinaz Koushanfar, Tajana Rosing
📗 PDF
🗒 SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation
👥 Khaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song, Dmitry Evtyushkin, Dmitry Ponomarev, Nael Abu-Ghazaleh
📗 PDF
🗒 Development of FEB Configuration Test Board for ATLAS NSW Upgrade
👥 Houbing Lu, Feng Li, Peng Miao, Kun Hu, Zhilei Zhang, Rongqi Sun, Qingli Ma, Ge Jin
📗 PDF
🗒 VLSI Design Of Advanced Digital Filters
👥 Rozita Teymourzadeh
📗 PDF
🗒 Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis
👥 Rozita Teymourzadeh, Mometo Jim Abigo, Mok Vee Hoong
📗 PDF
🗒 Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique
👥 Yazan Samir Algnabi, Furat A. Aldaamee, Rozita Teymourzadeh
📗 PDF
🗒 Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor
👥 Rozita Teymourzadeh, Memtode Jim, Mok Vee hong
📗 PDF
🗒 FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure
👥 Yazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman, Md Shabiul Islam
📗 PDF
🗒 Mitigating Wordline Crosstalk using Adaptive Trees of Counters
👥 Seyed Mohammad Seyedzadeh, Alex K. Jones, Rami Melhem
📗 PDF
🗒 CMOS: Dynamic Multi-key Obfuscation Structure for Strong PUFs
👥 Jiliang Zhang, Lu Wan
📗 PDF
🗒 Gemini: Reducing DRAM Cache Hit Latency by Hybrid Mappings
👥 Ye Chi
📗 PDF
🗒 Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems
👥 Xiaoyuan Wang
📗 PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
🗒 Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs
👥 Thomas B. Preußer
🗒 LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels
👥 Julian Stecklina, Thomas Prescher
🗒 A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB
👥 Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham
🗒 RAPIDNN: In-Memory Deep Neural Network Acceleration Framework
👥 Mohsen Imani, Mohammad Samragh, Yeseong Kim, Saransh Gupta, Farinaz Koushanfar, Tajana Rosing
🗒 SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation
👥 Khaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song, Dmitry Evtyushkin, Dmitry Ponomarev, Nael Abu-Ghazaleh
🗒 Development of FEB Configuration Test Board for ATLAS NSW Upgrade
👥 Houbing Lu, Feng Li, Peng Miao, Kun Hu, Zhilei Zhang, Rongqi Sun, Qingli Ma, Ge Jin
🗒 VLSI Design Of Advanced Digital Filters
👥 Rozita Teymourzadeh
🗒 Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis
👥 Rozita Teymourzadeh, Mometo Jim Abigo, Mok Vee Hoong
🗒 Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique
👥 Yazan Samir Algnabi, Furat A. Aldaamee, Rozita Teymourzadeh
🗒 Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor
👥 Rozita Teymourzadeh, Memtode Jim, Mok Vee hong
🗒 FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure
👥 Yazan Samir Algnabi, Rozita Teymourzadeh, Masuri Othman, Md Shabiul Islam
🗒 Mitigating Wordline Crosstalk using Adaptive Trees of Counters
👥 Seyed Mohammad Seyedzadeh, Alex K. Jones, Rami Melhem
🗒 CMOS: Dynamic Multi-key Obfuscation Structure for Strong PUFs
👥 Jiliang Zhang, Lu Wan
🗒 Gemini: Reducing DRAM Cache Hit Latency by Hybrid Mappings
👥 Ye Chi
🗒 Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems
👥 Xiaoyuan Wang
#HardwareArchitecture
AI Python & arXiv Channel
5 of Latest Published Articles:
Hardware Architecture
#HardwareArchitecture
🗒 BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
👥 Yaman Umuroglu, Lahiru Rasnayake, Magnus Sjalander
📗 PDF
🗒 Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs
👥 Thomas B. Preußer
📗 PDF
🗒 LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels
👥 Julian Stecklina, Thomas Prescher
📗 PDF
🗒 A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB
👥 Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham
📗 PDF
🗒 RAPIDNN: In-Memory Deep Neural Network Acceleration Framework
👥 Mohsen Imani, Mohammad Samragh, Yeseong Kim, Saransh Gupta, Farinaz Koushanfar, Tajana Rosing
📗 PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
🗒 BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
👥 Yaman Umuroglu, Lahiru Rasnayake, Magnus Sjalander
🗒 Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs
👥 Thomas B. Preußer
🗒 LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels
👥 Julian Stecklina, Thomas Prescher
🗒 A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB
👥 Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham
🗒 RAPIDNN: In-Memory Deep Neural Network Acceleration Framework
👥 Mohsen Imani, Mohammad Samragh, Yeseong Kim, Saransh Gupta, Farinaz Koushanfar, Tajana Rosing
#HardwareArchitecture
AI Python & arXiv Channel
5 of Latest Published Articles:
Hardware Architecture
#HardwareArchitecture
🗒 A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks
👥 Naveen Kumar Macha, Bhavana Tejaswini Repalle, Sandeep Geedipally, Rafael Rios, Mostafizur Rahman
📗 PDF
🗒 Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits
👥 Naveen Kumar Macha, Sandeep Geedipally, Bhavana Repalle, Md Arif Iqbal, Wafi Danesh, Mostafizur Rahman
📗 PDF
🗒 Best-Effort FPGA Programming: A Few Steps Can Go a Long Way
👥 Jason Cong, Zhenman Fang, Yuchen Hao, Peng Wei, Cody Hao Yu, Chen Zhang, Peipei Zhou
📗 PDF
🗒 FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
👥 Jeff Zhang, Siddharth Garg
📗 PDF
🗒 Neuro-memristive Circuits for Edge Computing: A review
👥 Olga Krestinskaya, Alex Pappachen James, Leon O. Chua
📗 PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
🗒 A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks
👥 Naveen Kumar Macha, Bhavana Tejaswini Repalle, Sandeep Geedipally, Rafael Rios, Mostafizur Rahman
🗒 Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits
👥 Naveen Kumar Macha, Sandeep Geedipally, Bhavana Repalle, Md Arif Iqbal, Wafi Danesh, Mostafizur Rahman
🗒 Best-Effort FPGA Programming: A Few Steps Can Go a Long Way
👥 Jason Cong, Zhenman Fang, Yuchen Hao, Peng Wei, Cody Hao Yu, Chen Zhang, Peipei Zhou
🗒 FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
👥 Jeff Zhang, Siddharth Garg
🗒 Neuro-memristive Circuits for Edge Computing: A review
👥 Olga Krestinskaya, Alex Pappachen James, Leon O. Chua
#HardwareArchitecture
AI Python & arXiv Channel
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5 of Latest Published Articles:
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🗒 XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference
👥 Francesco Conti, Pasquale Davide Schiavone, Luca Benini
📗 PDF
🗒 A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks
👥 Naveen Kumar Macha, Bhavana Tejaswini Repalle, Sandeep Geedipally, Rafael Rios, Mostafizur Rahman
📗 PDF
🗒 Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits
👥 Naveen Kumar Macha, Sandeep Geedipally, Bhavana Repalle, Md Arif Iqbal, Wafi Danesh, Mostafizur Rahman
📗 PDF
🗒 Best-Effort FPGA Programming: A Few Steps Can Go a Long Way
👥 Jason Cong, Zhenman Fang, Yuchen Hao, Peng Wei, Cody Hao Yu, Chen Zhang, Peipei Zhou
📗 PDF
🗒 FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
👥 Jeff Zhang, Siddharth Garg
📗 PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
🗒 XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference
👥 Francesco Conti, Pasquale Davide Schiavone, Luca Benini
🗒 A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks
👥 Naveen Kumar Macha, Bhavana Tejaswini Repalle, Sandeep Geedipally, Rafael Rios, Mostafizur Rahman
🗒 Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits
👥 Naveen Kumar Macha, Sandeep Geedipally, Bhavana Repalle, Md Arif Iqbal, Wafi Danesh, Mostafizur Rahman
🗒 Best-Effort FPGA Programming: A Few Steps Can Go a Long Way
👥 Jason Cong, Zhenman Fang, Yuchen Hao, Peng Wei, Cody Hao Yu, Chen Zhang, Peipei Zhou
🗒 FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design
👥 Jeff Zhang, Siddharth Garg
#HardwareArchitecture
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♨️ arXiv Channel
5 of Latest Published Articles:
Hardware Architecture
#HardwareArchitecture
🗒 CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement
👥 Vinson Young, Sanjay Kariyappa, Moinuddin K. Qureshi
📗 PDF
🗒 Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
👥 Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
📗 PDF
🗒 Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs
👥 Tobias Strauch
📗 PDF
🗒 Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++
👥 Tobias Strauch
📗 PDF
🗒 Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
👥 Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
📗 PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
🗒 CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement
👥 Vinson Young, Sanjay Kariyappa, Moinuddin K. Qureshi
🗒 Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
👥 Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
🗒 Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs
👥 Tobias Strauch
🗒 Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++
👥 Tobias Strauch
🗒 Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
👥 Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
#HardwareArchitecture
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Forwarded from arXiv
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📗 General Literature
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📗 Computer Science and Game Theory
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♨️ arXiv Channel
5 of Latest Published Articles:
Hardware Architecture
#HardwareArchitecture
🗒 MPNA: A Massively-Parallel Neural Array Accelerator with Dataflow Optimization for Convolutional Neural Networks
👥 Muhammad Abdullah Hanif, Rachmad Vidya Wicaksana Putra, Muhammad Tanvir, Rehan Hafiz, Semeen Rehman, Muhammad Shafique
📗 PDF
🗒 Neuromorphic hardware as a self-organizing computing system
👥 Lyes Khacef, Bernard Girau, Nicolas Rougier, Andres Upegui, Benoit Miramond
📗 PDF
🗒 Architectural exploration of heterogeneous memory systems
👥 M. Horro, G. Rodríguez, J. Touriño, M. T. Kandemir
📗 PDF
🗒 Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA
👥 Swagata Mandal, Sreetama Sarkar, Wong Ming Ming, Anupam Chattopadhyay, Amlan Chakrabarti
📗 PDF
🗒 Learning-based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems
👥 Biresh Kumar Joardar, Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, Radu Marculescu
📗 PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
🗒 MPNA: A Massively-Parallel Neural Array Accelerator with Dataflow Optimization for Convolutional Neural Networks
👥 Muhammad Abdullah Hanif, Rachmad Vidya Wicaksana Putra, Muhammad Tanvir, Rehan Hafiz, Semeen Rehman, Muhammad Shafique
🗒 Neuromorphic hardware as a self-organizing computing system
👥 Lyes Khacef, Bernard Girau, Nicolas Rougier, Andres Upegui, Benoit Miramond
🗒 Architectural exploration of heterogeneous memory systems
👥 M. Horro, G. Rodríguez, J. Touriño, M. T. Kandemir
🗒 Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA
👥 Swagata Mandal, Sreetama Sarkar, Wong Ming Ming, Anupam Chattopadhyay, Amlan Chakrabarti
🗒 Learning-based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems
👥 Biresh Kumar Joardar, Ryan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, Radu Marculescu
#HardwareArchitecture
AI Python & arXiv Channel