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π¦Makefile - Macros #NewTips
Program make allows you to use macros, which are similar to variables. Macros are defined in the Makefile as pairs =. An example was shown below -
MACROS = -me
PSROFF = groff -Tps
DITROFF = groff -Tdvi
CFLAGS = -O -systype bsd43
LIBS = "-lncurses -lm -lsdl"
MYFACE = ": *)"
Special macros
1) Before executing any command, certain special macros are predefined in the target ruleset -
$ @ Is the name of the file to create.
$? these are the names of the changed dependents.
$ @ Is the name of the file to create.
$? these are the names of the changed dependents.
2) For example, we can use the rule like this:
hello : main . cpp hello . cpp factorial . cpp
$ ( CC ) $ ( CFLAGS ) $ ? $ ( LDFLAGS ) - o $ @
3) Alternatively :
hello : main . cpp hello . cpp factorial . cpp
$ ( CC ) $ ( CFLAGS ) $ @ . cpp $ ( LDFLAGS ) - o $ @
In this example, $ @ represents hello and $? or $ @. cpp picks up all modified source files.
4) There are two other special macros used in implicit rules. They -
$ <name of the linked file that invoked the action.
$ * prefix common to target and dependent files.
$ <name of the linked file that invoked the action.
$ * prefix common to target and dependent files.
5) A general implicit rule is to create .o (object) files from .cpp (source files).
... cpp . o :
$ ( CC ) $ ( CFLAGS ) - c $ <
Alternatively :
... cpp . o :
$ ( CC ) $ ( CFLAGS ) - c $ *. c
π¦Defining custom suffix rules in the Makefile :
1) Make can automatically create the file using cc -c for the corresponding .c file. These rules are built into make , and you can take advantage of this to shorten your Makefile. If you only list the .h files in the dependency line of the Makefile that the current target depends on, make knows that the corresponding .cfile is already required. You don't need to include the command for the compiler.
2) This further reduces the Makefile as shown below -
OBJECTS = main.o hello.o factorial.o
hello: $ (OBJECTS)
cc $ (OBJECTS) -o hello
hellp.o: functions.h
main.o: functions.h
factorial.o: functions.h
3) Make uses a special target named .SUFFIXES, which allows you to define your own suffixes. For example, refer to the dependency line given below -
.SUFFIXES: .foo .bar
It tells make that you will use these special suffixes to create your own rules.
4) Just as make already knows how to make a .o file from a .c file , you can define rules like this:
.foo.bar:
tr '[AZ] [az]' '[NZ] [AM] [nz] [am]' <$ <> $ @
.co:
$ (CC) $ (CFLAGS) -c $ <
5) The first rule allows you to create a .bar file from a .foo file . This basically encrypts the file. The second rule is the default rule used by make to create an .o file from a .c file .
@undercodeTesting
β β β Uππ»βΊπ«Δπ¬πβ β β β
π¦Makefile - Macros #NewTips
Program make allows you to use macros, which are similar to variables. Macros are defined in the Makefile as pairs =. An example was shown below -
MACROS = -me
PSROFF = groff -Tps
DITROFF = groff -Tdvi
CFLAGS = -O -systype bsd43
LIBS = "-lncurses -lm -lsdl"
MYFACE = ": *)"
Special macros
1) Before executing any command, certain special macros are predefined in the target ruleset -
$ @ Is the name of the file to create.
$? these are the names of the changed dependents.
$ @ Is the name of the file to create.
$? these are the names of the changed dependents.
2) For example, we can use the rule like this:
hello : main . cpp hello . cpp factorial . cpp
$ ( CC ) $ ( CFLAGS ) $ ? $ ( LDFLAGS ) - o $ @
3) Alternatively :
hello : main . cpp hello . cpp factorial . cpp
$ ( CC ) $ ( CFLAGS ) $ @ . cpp $ ( LDFLAGS ) - o $ @
In this example, $ @ represents hello and $? or $ @. cpp picks up all modified source files.
4) There are two other special macros used in implicit rules. They -
$ <name of the linked file that invoked the action.
$ * prefix common to target and dependent files.
$ <name of the linked file that invoked the action.
$ * prefix common to target and dependent files.
5) A general implicit rule is to create .o (object) files from .cpp (source files).
... cpp . o :
$ ( CC ) $ ( CFLAGS ) - c $ <
Alternatively :
... cpp . o :
$ ( CC ) $ ( CFLAGS ) - c $ *. c
π¦Defining custom suffix rules in the Makefile :
1) Make can automatically create the file using cc -c for the corresponding .c file. These rules are built into make , and you can take advantage of this to shorten your Makefile. If you only list the .h files in the dependency line of the Makefile that the current target depends on, make knows that the corresponding .cfile is already required. You don't need to include the command for the compiler.
2) This further reduces the Makefile as shown below -
OBJECTS = main.o hello.o factorial.o
hello: $ (OBJECTS)
cc $ (OBJECTS) -o hello
hellp.o: functions.h
main.o: functions.h
factorial.o: functions.h
3) Make uses a special target named .SUFFIXES, which allows you to define your own suffixes. For example, refer to the dependency line given below -
.SUFFIXES: .foo .bar
It tells make that you will use these special suffixes to create your own rules.
4) Just as make already knows how to make a .o file from a .c file , you can define rules like this:
.foo.bar:
tr '[AZ] [az]' '[NZ] [AM] [nz] [am]' <$ <> $ @
.co:
$ (CC) $ (CFLAGS) -c $ <
5) The first rule allows you to create a .bar file from a .foo file . This basically encrypts the file. The second rule is the default rule used by make to create an .o file from a .c file .
@undercodeTesting
β β β Uππ»βΊπ«Δπ¬πβ β β β