⚡️ B0 DDR4 PCB (31.3mm compensated length)
The B0 UDIMM 2Rx8 PCB is a double sided PCB based off the A0 PCB. Like A0 this PCB suffers from poor package placement and most specifically poor DQ routing causing traces to be very long. As this PCB is based off the already quite garbage A0 PCB but it is dual rank, B0 is the worst DDR4 UDIMM non-ecc PCB. This PCB is so bad in fact that over 4000 can be near impossible with this PCB. Much Like A0, B0 is no longer produced for performance memory kits.
⚡️ B1 DDR4 PCB (16.3mm compensated length)
As there is no dual sided variant of the A1/D1 PCB B1 is confusingly a double sided 2Rx8 PCB based off the A2 PCB. Like A0 to B0, B1 is a worse PCB then A2 due to the complications of being dual rank. However this PCB is the best 2Rx8 PCB, with variants of this PCB being pushed over 5000mt/s.
⚡️ B2 DDR4 PCB
The B2 memory PCB is a dual sided 2Rx8 PCB based off the A3 PCB. Like with A2 to A3, B1 to B2 is a regression with the larger pad spacing causing worse routing. This PCB like A3 exists so that wide 16Gb packages can be used, with the maximum package size going from 9x13mm (B1) to 10.2x11mm (B2). This PCB like B1 is quite strong and can achieve 5000mt/s+.
#DDR4 #RAM_Guide
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The B0 UDIMM 2Rx8 PCB is a double sided PCB based off the A0 PCB. Like A0 this PCB suffers from poor package placement and most specifically poor DQ routing causing traces to be very long. As this PCB is based off the already quite garbage A0 PCB but it is dual rank, B0 is the worst DDR4 UDIMM non-ecc PCB. This PCB is so bad in fact that over 4000 can be near impossible with this PCB. Much Like A0, B0 is no longer produced for performance memory kits.
⚡️ B1 DDR4 PCB (16.3mm compensated length)
As there is no dual sided variant of the A1/D1 PCB B1 is confusingly a double sided 2Rx8 PCB based off the A2 PCB. Like A0 to B0, B1 is a worse PCB then A2 due to the complications of being dual rank. However this PCB is the best 2Rx8 PCB, with variants of this PCB being pushed over 5000mt/s.
⚡️ B2 DDR4 PCB
The B2 memory PCB is a dual sided 2Rx8 PCB based off the A3 PCB. Like with A2 to A3, B1 to B2 is a regression with the larger pad spacing causing worse routing. This PCB like A3 exists so that wide 16Gb packages can be used, with the maximum package size going from 9x13mm (B1) to 10.2x11mm (B2). This PCB like B1 is quite strong and can achieve 5000mt/s+.
#DDR4 #RAM_Guide
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DDR4 tRFC Telegram@HW_OC.png
100.9 KB
Possible tRFC values for DDR4 memory chips at any given frequency
In the case of unknown chips (but known manufacturers), you can guess the memory revision by finding the tRFC limit
Always check the up-to-date version from Hardwareluxx
#AMD #Intel #DDR4
#RAM_Guide
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In the case of unknown chips (but known manufacturers), you can guess the memory revision by finding the tRFC limit
Always check the up-to-date version from Hardwareluxx
#AMD #Intel #DDR4
#RAM_Guide
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Zen2_3 Ram Overclocking 101 Telegram@HW_OC.pdf
338.8 KB
📃 Zen 2 / Zen 3 Ram Overclocking 101
This guide provides memory overclocking starting points for various memory ICs, particularly useful for Ryzen 3000, 4000, and 5000 series processors, check out the main source for the most up-to-date version
#AMD #AM4 #DDR4
#Zen2 #Zen3
#RAM_Guide
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This guide provides memory overclocking starting points for various memory ICs, particularly useful for Ryzen 3000, 4000, and 5000 series processors, check out the main source for the most up-to-date version
#AMD #AM4 #DDR4
#Zen2 #Zen3
#RAM_Guide
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There are five fundamental operations that need to be performed when accessing data in DRAM
- Activation opens one of the DRAM rows in a bank, and copies the data of the opened row into the row buffer.
- Restoration ensures that the charge that is drained from each cell in the DRAM row during activation is restored to its full level, to prevent data loss.
- Reads and writes can be performed once the data of an activated row is copied to the row buffer.
- Precharge releases the data from the row buffer when the memory controller is done issuing reads and writes to the activated row, and prepares the bank to activate a different row.
#RAM_Guide
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- Activation opens one of the DRAM rows in a bank, and copies the data of the opened row into the row buffer.
- Restoration ensures that the charge that is drained from each cell in the DRAM row during activation is restored to its full level, to prevent data loss.
- Reads and writes can be performed once the data of an activated row is copied to the row buffer.
- Precharge releases the data from the row buffer when the memory controller is done issuing reads and writes to the activated row, and prepares the bank to activate a different row.
#RAM_Guide
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❤1
⚡️ P-States and C-States
Two control mechanisms exist to decrease the power consumption of a processor:
▫️Power down subsystems: C-States
▫️Voltage/Frequency reduction: P-States
C-States describe various idle (power saving) capabilities. Before a subsystem can be shut off, that subsystem should not be running anything, so it should be at idle—doing nothing, executing nothing. So C-state x (or Cx) means one or more subsystems of the CPU is at idle and powered down.
On the other hand, P-states execute switches to specific (power saving) states. The subsystem is actually running but does not require full performance, so the voltage and/or frequency it operates at is reduced. P-state x (or Px) means the subsystem it refers to (e.g., a CPU core) is operating at a specific (frequency and voltage) pair.
Because most modern CPUs have multiple cores in a single package, C-states are further divided into core C-states (CC-states) and package C-states (PC-states). The reason for PC-states is that there are other (shared) components in the processor that can also be powered down after all cores using them are powered down (e.g., the shared cache). However, as a user or programmer, we cannot control these since we do not interact with the package directly, but, rather, with the individual cores. We can then only affect the CC-states directly; PC-states are indirectly affected based on the CC-states of the cores.
The states are numbered, starting from zero, like C0, C1… and P0, P1... . The higher the number, the more power is saved. C0 means no power saving by shutting down something, so everything is powered on. P0 means maximum performance, thus maximum frequency, voltage, and power used.
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Two control mechanisms exist to decrease the power consumption of a processor:
▫️Power down subsystems: C-States
▫️Voltage/Frequency reduction: P-States
C-States describe various idle (power saving) capabilities. Before a subsystem can be shut off, that subsystem should not be running anything, so it should be at idle—doing nothing, executing nothing. So C-state x (or Cx) means one or more subsystems of the CPU is at idle and powered down.
On the other hand, P-states execute switches to specific (power saving) states. The subsystem is actually running but does not require full performance, so the voltage and/or frequency it operates at is reduced. P-state x (or Px) means the subsystem it refers to (e.g., a CPU core) is operating at a specific (frequency and voltage) pair.
Because most modern CPUs have multiple cores in a single package, C-states are further divided into core C-states (CC-states) and package C-states (PC-states). The reason for PC-states is that there are other (shared) components in the processor that can also be powered down after all cores using them are powered down (e.g., the shared cache). However, as a user or programmer, we cannot control these since we do not interact with the package directly, but, rather, with the individual cores. We can then only affect the CC-states directly; PC-states are indirectly affected based on the CC-states of the cores.
The states are numbered, starting from zero, like C0, C1… and P0, P1... . The higher the number, the more power is saved. C0 means no power saving by shutting down something, so everything is powered on. P0 means maximum performance, thus maximum frequency, voltage, and power used.
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⚡️ HWiNFO Author Martin Writes About The Importance of Core Effective Clocks
"It has become a common practice for several years to report instant (discrete) clock values for CPUs. This method is based on knowledge of the actual bus clock (BCLK) and sampling of core ratios at specific time points. The resulting clock is then a simple result of ratio times BCLK. Such approach worked quite well in the past, but is not longer sufficient. Over the years, CPUs have become very dynamic components that can change their operating parameters hundreds of times per second depending on several factors including workload amount, temperature limits, thermal/VR current and power limits, turbo ratios, dynamic TDP, etc. While this method still represents actual clock values and ratios reported match defined P-States, it has become insufficient to provide a good overview of CPU dynamics, especially when parameters are fluctuating with a much higher frequency than any software is able to capture. Another disadvantage is that cores in modern CPUs that have no workload are being suspended (lower C-States). In such case when software attempts to poll their status, it will wake them up briefly and thus the clock obtained doesn't respect the sleeping state.
Hence a new approach needs to be used called the Effective clock. This method relies on hardware's capability to sample the actual clock state (all its levels) across a certain interval, including sleeping (halted) states. The software then queries the counter over a specific polling period, which provides the average value of all clock states that occurred in the given interval. HWiNFO v6.13-3955 Beta introduces reporting of this clock. Many users might be surprised how different this clock is in comparison to the traditional clock values reported. But please note that this effective value is the average clock across the polling interval used in HWiNFO. This new method has been tested on several CPUs and has shown to provide more accurate results especially in scenarios with extremely fluctuating values.
On "Zen 2" (Matisse) systems this method can provide results closer to Ryzen Master (RM) per-core clock values, especially because it respects sleeping cores. It is assumed that such cores are marked as sleeping by RM when the effective (average) clock is below a certain threshold (somewhere around 50 MHz and below). Please note, that RM uses a different (proprietary) technique to measure clocks, so there might be some differences between the effective clock in HWiNFO and RM. While we work with AMD on the best way to access more accurate data to measure clock and voltage values, this remains the only method. Additionally, the current effective clock method is an architectural feature meaning that it doesn't depend on a certain CPU model, but is rather universal across a broad range of CPU families."
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"It has become a common practice for several years to report instant (discrete) clock values for CPUs. This method is based on knowledge of the actual bus clock (BCLK) and sampling of core ratios at specific time points. The resulting clock is then a simple result of ratio times BCLK. Such approach worked quite well in the past, but is not longer sufficient. Over the years, CPUs have become very dynamic components that can change their operating parameters hundreds of times per second depending on several factors including workload amount, temperature limits, thermal/VR current and power limits, turbo ratios, dynamic TDP, etc. While this method still represents actual clock values and ratios reported match defined P-States, it has become insufficient to provide a good overview of CPU dynamics, especially when parameters are fluctuating with a much higher frequency than any software is able to capture. Another disadvantage is that cores in modern CPUs that have no workload are being suspended (lower C-States). In such case when software attempts to poll their status, it will wake them up briefly and thus the clock obtained doesn't respect the sleeping state.
Hence a new approach needs to be used called the Effective clock. This method relies on hardware's capability to sample the actual clock state (all its levels) across a certain interval, including sleeping (halted) states. The software then queries the counter over a specific polling period, which provides the average value of all clock states that occurred in the given interval. HWiNFO v6.13-3955 Beta introduces reporting of this clock. Many users might be surprised how different this clock is in comparison to the traditional clock values reported. But please note that this effective value is the average clock across the polling interval used in HWiNFO. This new method has been tested on several CPUs and has shown to provide more accurate results especially in scenarios with extremely fluctuating values.
On "Zen 2" (Matisse) systems this method can provide results closer to Ryzen Master (RM) per-core clock values, especially because it respects sleeping cores. It is assumed that such cores are marked as sleeping by RM when the effective (average) clock is below a certain threshold (somewhere around 50 MHz and below). Please note, that RM uses a different (proprietary) technique to measure clocks, so there might be some differences between the effective clock in HWiNFO and RM. While we work with AMD on the best way to access more accurate data to measure clock and voltage values, this remains the only method. Additionally, the current effective clock method is an architectural feature meaning that it doesn't depend on a certain CPU model, but is rather universal across a broad range of CPU families."
Join @HW_OC ⚡️