VerifWorks Hiring DV and RTL Engineer with 2+ Yrs Exp

Notice Period: Immediate to 30 days

Interested kindly share your updated profile to rama@verifworks.com
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Great opportunity to work with Sevitech systems (A #UST Company) is looking for

 #RTL #Design #ASIC #engineers from #2 yrs to #3 yrs for a team-based model & #longterm -term #projects , can support from #Bangalore #india.,
should be able to join in 30 days to 90days (as per the project urgency).
3Experience in micro-architecture development, #RTL design, #frontend flows (#Lint, #CDC, #lowpower checks, etc.)
-Worked on one or more protocols like good understanding of protocols like #usb , #ufs , #pcie , #DSI, #CSI, etc. is desirable..
Interested engineers kindly get in touch on  #Bhagyalakshmi.Muthuramalingam@ust.com
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For fresehrs 👍 All the best

AMD Hires for #SOCVerification Lead #Lowpower
Exp:10-18Yrs
Location:#Bangalore/ #Hyderabad
Interested applicants can share resume to Supraja.Boyapati@amd.com

https://lnkd.in/dgMNn2ry

We are hiring...! Its Great opportunity to Join Wipro VLSI Design.
Looking for ASIC/RTL Engineers/Leads with experience 4 to 15 years
Job Location: Bangalore/Hyderabad/Kochi/Chennai/Pune/Ahmedabad/Noida
Job Type: Permanent
Joining Time: Immediate to 60 days
Please share your profile to pavan.v01@wipro.com

Job opportunity! Senior Analog IC Design Engineer - Optical Sensing, 90k-120k Swiss Francs - #Neuchâtel.

This is an opportunity for an Analog/ Design Engineer to join an established Semiconductor manufacturer developing ultra-low power ICs for a range of automotive and consumer applications. Based in their design centre located in the scenic area of the French speaking part of Switzerland.

Interested? Click the link to apply or email: leon.morrison@ic-resources.com