DRILLING DOWN INTO THE SIPEARL EUROPEAN ARM SERVER CHIP
The EU develops it's own server processor, both for general purposes and exascale computing. Matrix math and FPGA accelerators also coming from European suppliers.
Initiative is driving now by SiPearl, France bases start-up, just rai
Philippe Notton, CEO and founder, tells The Next Platform, the number of engineers working on the SiPearl Arm server chips – Rhea is the first generation and Chronos is the second generation – will grow to around 200 over the next two years as Rhea is created, tested, and ramped.
As to why Arm and not another core? For RISC-V, it is too early, and definitely so for a general purpose processor. X86 is not officially licensable and it is a bit too US-centric for what we are doing. And for us, Arm is much more neutral and what they are doing for HPC makes a lot of sense.”
The Rhea chip will support both DDR4 and DDR5 main memory as well as HBM main memory, PCI-Express 5.0 peripheral controllers and will support the CCIX protocol for hoking up accelerators over PCI-Express.
More about EPI
https://www.european-processor-initiative.eu/general-purpose-processor/
The EU develops it's own server processor, both for general purposes and exascale computing. Matrix math and FPGA accelerators also coming from European suppliers.
Initiative is driving now by SiPearl, France bases start-up, just rai
Philippe Notton, CEO and founder, tells The Next Platform, the number of engineers working on the SiPearl Arm server chips – Rhea is the first generation and Chronos is the second generation – will grow to around 200 over the next two years as Rhea is created, tested, and ramped.
As to why Arm and not another core? For RISC-V, it is too early, and definitely so for a general purpose processor. X86 is not officially licensable and it is a bit too US-centric for what we are doing. And for us, Arm is much more neutral and what they are doing for HPC makes a lot of sense.”
The Rhea chip will support both DDR4 and DDR5 main memory as well as HBM main memory, PCI-Express 5.0 peripheral controllers and will support the CCIX protocol for hoking up accelerators over PCI-Express.
More about EPI
https://www.european-processor-initiative.eu/general-purpose-processor/
The Next Platform
Drilling Down Into The SiPearl European Arm Server Chip
The European Union has made it clear that it wants to be able to stand on its own two feet in the design of server processors, for both general purpose
RISC-V V-extension (Vectorized or SIMD instructions extension) exploration by EPI
European Processor Initiative
V for vector: software exploration of the vector extension of RISC-V - European Processor Initiative
Introduction The European Processor Initiative (EPI) is building a new central processing unit (CPU) with European technology. This CPU will bundle an accelerator, based on the open source RISC-V architecture. This accelerator will include support for the…
For Russian speaking only, sorry for inconvenience
Russian telecom company Metrotek announced session of online webinars "Introduction to FPGA development".
This course is for beginners and free of charge. The very first lecture starts at 11th of May. See details below:
https://habr.com/ru/post/500770
Take a part if you wish don't look stupid with question "How can I launch my cpp code on FPGA" :)
PS: It's not a commercial promo, if you wish to share similar trainings in English, we will do it with pleasure.
Russian telecom company Metrotek announced session of online webinars "Introduction to FPGA development".
This course is for beginners and free of charge. The very first lecture starts at 11th of May. See details below:
https://habr.com/ru/post/500770
Take a part if you wish don't look stupid with question "How can I launch my cpp code on FPGA" :)
PS: It's not a commercial promo, if you wish to share similar trainings in English, we will do it with pleasure.
Хабр
Приглашаем на вебинар про FPGA для начинающих
Приветствую! Хочу сообщить, что скоро мы начинаем бесплатный online курс по FPGA! Первая лекция курса пройдёт 11 мая, начало в 18:00 на канале Twitch MaksimTolkachev. Всю информацию о курсе Вы можете...
NVIDIA released A100 TENSOR CORE GPU
TPUv3 be like :)
Some key features
- Sparsity optimized tensorcore
- 40 GB HBM2 and 40 MB L2 cache
- Multi-Instance GPU (MIG)
- Third-generation NVLink has a data rate of 50 Gbit/sec per signal pair, nearly doubling the 25.78 Gbits/sec rate in V100
- Support for NVIDIA Magnum IO and Mellanox interconnect solutions
YouTube presentation by CEO Jensen Huang
Technical Details
TPUv3 be like :)
Some key features
- Sparsity optimized tensorcore
- 40 GB HBM2 and 40 MB L2 cache
- Multi-Instance GPU (MIG)
- Third-generation NVLink has a data rate of 50 Gbit/sec per signal pair, nearly doubling the 25.78 Gbits/sec rate in V100
- Support for NVIDIA Magnum IO and Mellanox interconnect solutions
YouTube presentation by CEO Jensen Huang
Technical Details
YouTube
NVIDIA GTC May 2020 Keynote Pt6: NVIDIA A100 Data Center GPU Based on NVIDIA Ampere Architecture
NVIDIA CEO Jensen Huang introduces the NVIDIA A100 data center GPU, which dramatically increases throughput of scale-out and scale-up applications whether for data analytics, training or inference. The A100 delivers 1.5 terabytes per second of bandwidth thanks…