FPU Generator - a Floating Point Adder/Multiplier/Multiply-Accumulate generator and testbench.

Links:
▫️ Sources

#perl #matlab #FPU #FloatingPoint
@ipcores

SimpleVOut - FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

Links:
▫️ Sources

#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
@ipcores

Vortex - a full-system RISCV-based GPGPU processor.

Specs
▫️Support RISC-V RV32I ISA
▫️Fully scalable: 1 to 16 cores with optional L2 and L3 caches
▫️OpenCL 1.2 Support
▫️FPGA target: Intel Arria 10 @200 MHz

💾 https://github.com/himanshu5-prog/vortexGPU

#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores

LoRa Modulator - a custom LoRa modulator that supports different bandwidths and spreading factors (SF) on Lattice ECP5 FPGA and I/Q interface with AT86RF215 RF radio.

💾 https://github.com/uw-x/lora-modulator

#verilog #RF #LoRa #modulator #transmitter
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Process-Voltage-Temperature (PVT) Sensors with MCU - a collection of open-source circuits and software tools for PVT monitoring in custom ICs.

💾 https://github.com/scale-lab/PVTsensors

#verilog #asic #PVT #cmos #RISCV #precess
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XiangShan - mature (almost 6000 commits) high-performance RISC-V processor by Institute of Computing Technology, Chinese Academy of Sciences.

💾 https://github.com/OpenXiangShan/XiangShan
📄 https://github.com/OpenXiangShan/XiangShan-doc

#ISA #RISCV #scala #chisel #CPU #FPU
@ipcores

S-Link - a lightweight chiplet/chip-to-chip controller. S-Link is a simple, scalable, and flexible link controller protocol geared towards chiplets and chip-to-chip communication.

S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.

Features:
▫️Mult-lane support (upto 128+)
▫️128b/130b encoding
▫️Parameterizable Application Data Widths
▫️Configurable Attributes for fine tuning link controls and/or active link management
▫️ECC/CRC for error checking of packet headers and payload data
▫️Parameterizable pipeline stages to optimize for frequency and/or power

💾 https://github.com/waviousllc/wav-slink-hw

#chiplet #protocol #verilog
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700 followers 😱
Thank you to everyone of you! 🙏🏻

Vortex - a full-system RISCV-based GPGPU processor

Specs
▫️Support RISC-V RV32IMF ISA
▫️Fully scalable: 1 to 32 cores with optional L2 and L3 caches
▫️OpenCL 1.2 Support
▫️FPGA target: Intel Arria 10 @200 MHz

💾 https://github.com/vortexgpgpu/vortex

#verilog #GPGPU #GPU #FPGA #LLVM
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Cryptography IP-cores lib
Used openSSL as reference models to check the correctness of the implementation.

Features:
▫️DES
▫️AES
▫️CTR-AES
▫️CBC-AES
▫️CBC-DES
▫️CBC-TDES

💾 https://github.com/tmeissner/cryptocores

#сryptography #vhdl #verilog #aes #cipher #OSVVM
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SVLogger - A SystemVerilog logger to help designers to log events in a circuit during a simulation in a consistent way. SVLogger is a simple class, easy to instantiate and use, with no dependencies.

💾 https://github.com/dpretet/svlogger
📄 https://github.com/dpretet/svlogger/tree/main/example

#logger #logging #simulation #verification #debug #sv #systemverilog #icarus
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SURF (SLAC Ultimate RTL Framework) - a huge VHDL library for FPGA development.

Links:
▫️ sources
▫️ documentation

#VHDL #library #STL #primitives
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open5G_rx - a synthesizable verilog HDL core for a 5G NR lower phy receiver.

Implemented:
▫️ Decimator
▫️ PSS correlator
▫️ Peak detector
▫️ PSS detector
▫️ FFT demodulator
▫️ SSS detector
▫️ Frame sync
▫️ Channel estimator
▫️ Ressource grid subscriber
▫️ AXI-DMAC


💾 https://github.com/catkira/open5G_rx

#SV #5G #DSP #FFT #ORAN
@ipcores

openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design.

Features:
▫️802.11a/g/n [IEEE 802.11n (Wi-Fi 4)]
▫️20MHz bandwidth; 70 MHz to 6 GHz frequency range
▫️Mode tested: Ad-hoc; Station; AP, Monitor
▫️DCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)
▫️802.11 packet injection and fuzzing
▫️CSI: Channel State Information, freq offset, equalizer to computer
▫️CSI fuzzer: Create artificial channel response in WiFi transmitter
▫️CSI radar: Moving detection. Joint radar and communication
▫️IQ capture: real-time AGC, RSSI, IQ sample to computer
▫️Configurable channel access priority parameters
▫️Time slicing based on MAC address (time gated/scheduled FPGA queues)
▫️Easy to change bandwidth and frequency:
▫️2MHz for 802.11ah
▫️10MHz for 802.11p

Links:
📄 https://github.com/open-sdr/openwifi
💾 https://github.com/open-sdr/openwifi-hw

#SV #80211 #SDR #DSP #wifi
@ipcores

SlowDDR3 - A general slow DDR3 interface.

Features:
▫️Very little resource consumption*
▫️Suits for all FPGAs with 1.5V IO voltage
▫️Designed to run at DDR-100
▫️Designed to work with LVCMOS IO PADs
▫️Write in SpinalHDL (Future is coming 😅)

*E.g. Gowin DDR3 IP consumes 1288 FFs, 1363 LUTs, 102 ALUs, 8 BSRAMs and 110 SSRAMs.
While slowDDR3 consumes 147 FFs and 216 LUTs.

Links:
💾 src: https://github.com/ZiyangYE/General-Slow-DDR3-Interface
📄 example: https://github.com/ZiyangYE/LicheeTang20K_DDR_Test

#DDR3 #SDRAM #SpinalHDL
@ipcores

USB_CDC - Full Speed (12Mbit/s) USB communications device class (or USB CDC class) for FPGA and ASIC designs.

USB_CDC implements the Abstract Control Model (ACM) subclass. Windows 10 provides a built-in driver (Usbser.sys) for USB CDC devices. A USB_CDC device is automatically recognized by Windows 10 as a virtual COM port, and a serial port terminal application such as CoolTerm can be used to communicate with it.

macOS and Linux provide built-in drivers for USB CDC ACM devices too. On macOS, the virtual COM gets a name like /dev/cu.usbmodem14601, whereas, on Linux, it gets a name like /dev/ttyACM0.

💾 https://github.com/ulixxe/usb_cdc

#USB #CDC #UART #verilog
@ipcores

USB_HID_host - a compact USB HID host FPGA core supporting keyboards, mice and gamepads.

It is designed mainly for FPGA retro gaming and computing projects. The most significant advantage is its all-in-one design. It does not require a CPU to work. And it is quite small (<300 LUTs, <250 registers and 1 BRAM block).

Features:
▫️No CPU is required. The core handles all layers of the USB protocol related to HID devices
▫️No USB interface IC (PHY) needed
▫️USB low-speed (1.5Mbps). Uses a single 12Mhz clock

💾 https://github.com/nand2mario/usb_hid_host

#USB #HID #host #verilog
@ipcores

FPGA USB-device - USB full-speed device core to implement. It requires only 3 FPGA common IOs rather than additional chips.

Features:
▫️Pure Verilog implementation
▫️Implementation of USB-serial, USB-MSD, USB-camera, USB-audio, USB-hid, etc
▫️The circuit is simple: three FPGA pins, one resistor and one USB connector

💾 https://github.com/WangXuan95/FPGA-USB-Device

#USB #HID #MSD #UVC #CDC #device #verilog
@ipcores

An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components

In this work, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured.

Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC.

The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3.

Links:
💾 https://github.com/LukiLeu/FPGA_ADC
📄 https://dl.acm.org/doi/10.1145/3431920.3439287

#ADC #VHDL #TDC
@ipcores

Send video/audio over HDMI on an FPGA

SystemVerilog code for HDMI 1.4b video/audio output on an FPGA.

Features
▫️ 24-bit color
▫️ Data island packets
▫️ Null packet
▫️ ECC with BCH systematic encoding GF(2^8)
▫️ Audio clock regeneration
▫️ L-PCM audio 2-channel
▫️ Audio InfoFrame
▫️ Video formats 1, 2, 3, 4, 16, 17, 18, 19
▫️ VGA text mode
▫️ IBM 8x16 font
▫️ Double Data Rate I/O (DDRIO)
▫️ Supports up to 3840x2160@30Hz

Links
💾 https://github.com/hdl-util/hdmi
📄 https://purisa.me/blog/hdmi-released/

#HDMI #video #SV #SystemVerilog
@ipcores

FPGA-FFT - a highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

Features
▫️Data input/output are continuous with no gaps between frames
▫️Support power-of-two sizes
▫️Support fixed point data
▫️Resource usage is on par with Xilinx FFT IP core
▫️Fmax is up to 30% higher for common sizes than Xilinx FFT IP core

Links
💾 https://github.com/owocomm-0/fpga-fft

#fft #dsp #vhdl #xilinx
@ipcores