Verilog LFSR - Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation.
β«οΈ
β«οΈ
β«οΈ
β«οΈ
β«οΈ
β«οΈ
Links:
β«οΈ Sources
#verilog #python #MyHDL #LFSR #CRC
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β«οΈ
lfsr.v - Parametrizable combinatorial LFSR/CRC moduleβ«οΈ
lfsr_crc.v - Parametrizable CRC computation wrapperβ«οΈ
lfsr_descramble.v - Parametrizable LFSR self-synchronizing descramblerβ«οΈ
lfsr_prbs_check.v - Parametrizable PRBS checker wrapperβ«οΈ
lfsr_prbs_gen.v - Parametrizable PRBS generator wrapperβ«οΈ
lfsr_scramble.v - Parametrizable LFSR self-synchronizing scramblerLinks:
β«οΈ Sources
#verilog #python #MyHDL #LFSR #CRC
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π1
SimpleVOut - FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See
Links:
β«οΈ Sources
#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
@ipcores
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See
svo_defines.vh for details on those parameters.Links:
β«οΈ Sources
#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
@ipcores
π1π1
Vortex - a full-system RISCV-based GPGPU processor.
Specs
β«οΈSupport RISC-V RV32I ISA
β«οΈFully scalable: 1 to 16 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/himanshu5-prog/vortexGPU
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
Specs
β«οΈSupport RISC-V RV32I ISA
β«οΈFully scalable: 1 to 16 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/himanshu5-prog/vortexGPU
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
π1
LoRa Modulator - a custom LoRa modulator that supports different bandwidths and spreading factors (SF) on Lattice ECP5 FPGA and I/Q interface with AT86RF215 RF radio.
πΎ https://github.com/uw-x/lora-modulator
#verilog #RF #LoRa #modulator #transmitter
@ipcores
πΎ https://github.com/uw-x/lora-modulator
#verilog #RF #LoRa #modulator #transmitter
@ipcores
XiangShan - mature (almost 6000 commits) high-performance RISC-V processor by Institute of Computing Technology, Chinese Academy of Sciences.
πΎ https://github.com/OpenXiangShan/XiangShan
π https://github.com/OpenXiangShan/XiangShan-doc
#ISA #RISCV #scala #chisel #CPU #FPU
@ipcores
πΎ https://github.com/OpenXiangShan/XiangShan
π https://github.com/OpenXiangShan/XiangShan-doc
#ISA #RISCV #scala #chisel #CPU #FPU
@ipcores
S-Link - a lightweight chiplet/chip-to-chip controller. S-Link is a simple, scalable, and flexible link controller protocol geared towards chiplets and chip-to-chip communication.
S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.
Features:
β«οΈMult-lane support (upto 128+)
β«οΈ128b/130b encoding
β«οΈParameterizable Application Data Widths
β«οΈConfigurable Attributes for fine tuning link controls and/or active link management
β«οΈECC/CRC for error checking of packet headers and payload data
β«οΈParameterizable pipeline stages to optimize for frequency and/or power
πΎ https://github.com/waviousllc/wav-slink-hw
#chiplet #protocol #verilog
@ipcores
S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.
Features:
β«οΈMult-lane support (upto 128+)
β«οΈ128b/130b encoding
β«οΈParameterizable Application Data Widths
β«οΈConfigurable Attributes for fine tuning link controls and/or active link management
β«οΈECC/CRC for error checking of packet headers and payload data
β«οΈParameterizable pipeline stages to optimize for frequency and/or power
πΎ https://github.com/waviousllc/wav-slink-hw
#chiplet #protocol #verilog
@ipcores
π5
700 followers π±
Thank you to everyone of you! ππ»
Thank you to everyone of you! ππ»
Vortex - a full-system RISCV-based GPGPU processor
Specs
β«οΈSupport RISC-V RV32IMF ISA
β«οΈFully scalable: 1 to 32 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/vortexgpgpu/vortex
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
Specs
β«οΈSupport RISC-V RV32IMF ISA
β«οΈFully scalable: 1 to 32 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/vortexgpgpu/vortex
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
π2β€1
Cryptography IP-cores lib
Used openSSL as reference models to check the correctness of the implementation.
Features:
β«οΈDES
β«οΈAES
β«οΈCTR-AES
β«οΈCBC-AES
β«οΈCBC-DES
β«οΈCBC-TDES
πΎ https://github.com/tmeissner/cryptocores
#Ρryptography #vhdl #verilog #aes #cipher #OSVVM
@ipcores
Used openSSL as reference models to check the correctness of the implementation.
Features:
β«οΈDES
β«οΈAES
β«οΈCTR-AES
β«οΈCBC-AES
β«οΈCBC-DES
β«οΈCBC-TDES
πΎ https://github.com/tmeissner/cryptocores
#Ρryptography #vhdl #verilog #aes #cipher #OSVVM
@ipcores
π3π₯1
SVLogger - A SystemVerilog logger to help designers to log events in a circuit during a simulation in a consistent way. SVLogger is a simple class, easy to instantiate and use, with no dependencies.
πΎ https://github.com/dpretet/svlogger
π https://github.com/dpretet/svlogger/tree/main/example
#logger #logging #simulation #verification #debug #sv #systemverilog #icarus
@ipcores
πΎ https://github.com/dpretet/svlogger
π https://github.com/dpretet/svlogger/tree/main/example
#logger #logging #simulation #verification #debug #sv #systemverilog #icarus
@ipcores
SURF (SLAC Ultimate RTL Framework) - a huge VHDL library for FPGA development.
Links:
β«οΈ sources
β«οΈ documentation
#VHDL #library #STL #primitives
@ipcores
Links:
β«οΈ sources
β«οΈ documentation
#VHDL #library #STL #primitives
@ipcores
π₯11π8π€1π1
open5G_rx - a synthesizable verilog HDL core for a 5G NR lower phy receiver.
Implemented:
β«οΈ Decimator
β«οΈ PSS correlator
β«οΈ Peak detector
β«οΈ PSS detector
β«οΈ FFT demodulator
β«οΈ SSS detector
β«οΈ Frame sync
β«οΈ Channel estimator
β«οΈ Ressource grid subscriber
β«οΈ AXI-DMAC
πΎ https://github.com/catkira/open5G_rx
#SV #5G #DSP #FFT #ORAN
@ipcores
Implemented:
β«οΈ Decimator
β«οΈ PSS correlator
β«οΈ Peak detector
β«οΈ PSS detector
β«οΈ FFT demodulator
β«οΈ SSS detector
β«οΈ Frame sync
β«οΈ Channel estimator
β«οΈ Ressource grid subscriber
β«οΈ AXI-DMAC
πΎ https://github.com/catkira/open5G_rx
#SV #5G #DSP #FFT #ORAN
@ipcores
π11β€4π₯4π±4β‘1
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design.
Features:
β«οΈ802.11a/g/n [IEEE 802.11n (Wi-Fi 4)]
β«οΈ20MHz bandwidth; 70 MHz to 6 GHz frequency range
β«οΈMode tested: Ad-hoc; Station; AP, Monitor
β«οΈDCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)
β«οΈ802.11 packet injection and fuzzing
β«οΈCSI: Channel State Information, freq offset, equalizer to computer
β«οΈCSI fuzzer: Create artificial channel response in WiFi transmitter
β«οΈCSI radar: Moving detection. Joint radar and communication
β«οΈIQ capture: real-time AGC, RSSI, IQ sample to computer
β«οΈConfigurable channel access priority parameters
β«οΈTime slicing based on MAC address (time gated/scheduled FPGA queues)
β«οΈEasy to change bandwidth and frequency:
β«οΈ2MHz for 802.11ah
β«οΈ10MHz for 802.11p
Links:
π https://github.com/open-sdr/openwifi
πΎ https://github.com/open-sdr/openwifi-hw
#SV #80211 #SDR #DSP #wifi
@ipcores
Features:
β«οΈ802.11a/g/n [IEEE 802.11n (Wi-Fi 4)]
β«οΈ20MHz bandwidth; 70 MHz to 6 GHz frequency range
β«οΈMode tested: Ad-hoc; Station; AP, Monitor
β«οΈDCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)
β«οΈ802.11 packet injection and fuzzing
β«οΈCSI: Channel State Information, freq offset, equalizer to computer
β«οΈCSI fuzzer: Create artificial channel response in WiFi transmitter
β«οΈCSI radar: Moving detection. Joint radar and communication
β«οΈIQ capture: real-time AGC, RSSI, IQ sample to computer
β«οΈConfigurable channel access priority parameters
β«οΈTime slicing based on MAC address (time gated/scheduled FPGA queues)
β«οΈEasy to change bandwidth and frequency:
β«οΈ2MHz for 802.11ah
β«οΈ10MHz for 802.11p
Links:
π https://github.com/open-sdr/openwifi
πΎ https://github.com/open-sdr/openwifi-hw
#SV #80211 #SDR #DSP #wifi
@ipcores
β€9π5β‘4π₯2β€βπ₯1
SlowDDR3 - A general slow DDR3 interface.
Features:
β«οΈVery little resource consumption*
β«οΈSuits for all FPGAs with 1.5V IO voltage
β«οΈDesigned to run at DDR-100
β«οΈDesigned to work with LVCMOS IO PADs
β«οΈWrite in SpinalHDL (Future is coming π )
*E.g. Gowin DDR3 IP consumes 1288 FFs, 1363 LUTs, 102 ALUs, 8 BSRAMs and 110 SSRAMs.
While slowDDR3 consumes 147 FFs and 216 LUTs.
Links:
πΎ src: https://github.com/ZiyangYE/General-Slow-DDR3-Interface
π example: https://github.com/ZiyangYE/LicheeTang20K_DDR_Test
#DDR3 #SDRAM #SpinalHDL
@ipcores
Features:
β«οΈVery little resource consumption*
β«οΈSuits for all FPGAs with 1.5V IO voltage
β«οΈDesigned to run at DDR-100
β«οΈDesigned to work with LVCMOS IO PADs
β«οΈWrite in SpinalHDL (Future is coming π )
*E.g. Gowin DDR3 IP consumes 1288 FFs, 1363 LUTs, 102 ALUs, 8 BSRAMs and 110 SSRAMs.
While slowDDR3 consumes 147 FFs and 216 LUTs.
Links:
πΎ src: https://github.com/ZiyangYE/General-Slow-DDR3-Interface
π example: https://github.com/ZiyangYE/LicheeTang20K_DDR_Test
#DDR3 #SDRAM #SpinalHDL
@ipcores
π₯5π3β€1β€βπ₯1π1
USB_CDC - Full Speed (12Mbit/s) USB communications device class (or USB CDC class) for FPGA and ASIC designs.
USB_CDC implements the Abstract Control Model (ACM) subclass. Windows 10 provides a built-in driver (
macOS and Linux provide built-in drivers for USB CDC ACM devices too. On macOS, the virtual COM gets a name like
πΎ https://github.com/ulixxe/usb_cdc
#USB #CDC #UART #verilog
@ipcores
USB_CDC implements the Abstract Control Model (ACM) subclass. Windows 10 provides a built-in driver (
Usbser.sys) for USB CDC devices. A USB_CDC device is automatically recognized by Windows 10 as a virtual COM port, and a serial port terminal application such as CoolTerm can be used to communicate with it.macOS and Linux provide built-in drivers for USB CDC ACM devices too. On macOS, the virtual COM gets a name like
/dev/cu.usbmodem14601, whereas, on Linux, it gets a name like /dev/ttyACM0.πΎ https://github.com/ulixxe/usb_cdc
#USB #CDC #UART #verilog
@ipcores
π19π₯8π1
USB_HID_host - a compact USB HID host FPGA core supporting keyboards, mice and gamepads.
It is designed mainly for FPGA retro gaming and computing projects. The most significant advantage is its all-in-one design. It does not require a CPU to work. And it is quite small (<300 LUTs, <250 registers and 1 BRAM block).
Features:
β«οΈNo CPU is required. The core handles all layers of the USB protocol related to HID devices
β«οΈNo USB interface IC (PHY) needed
β«οΈUSB low-speed (1.5Mbps). Uses a single 12Mhz clock
πΎ https://github.com/nand2mario/usb_hid_host
#USB #HID #host #verilog
@ipcores
It is designed mainly for FPGA retro gaming and computing projects. The most significant advantage is its all-in-one design. It does not require a CPU to work. And it is quite small (<300 LUTs, <250 registers and 1 BRAM block).
Features:
β«οΈNo CPU is required. The core handles all layers of the USB protocol related to HID devices
β«οΈNo USB interface IC (PHY) needed
β«οΈUSB low-speed (1.5Mbps). Uses a single 12Mhz clock
πΎ https://github.com/nand2mario/usb_hid_host
#USB #HID #host #verilog
@ipcores
π17β€2
FPGA USB-device - USB full-speed device core to implement. It requires only 3 FPGA common IOs rather than additional chips.
Features:
β«οΈPure Verilog implementation
β«οΈImplementation of USB-serial, USB-MSD, USB-camera, USB-audio, USB-hid, etc
β«οΈThe circuit is simple: three FPGA pins, one resistor and one USB connector
πΎ https://github.com/WangXuan95/FPGA-USB-Device
#USB #HID #MSD #UVC #CDC #device #verilog
@ipcores
Features:
β«οΈPure Verilog implementation
β«οΈImplementation of USB-serial, USB-MSD, USB-camera, USB-audio, USB-hid, etc
β«οΈThe circuit is simple: three FPGA pins, one resistor and one USB connector
πΎ https://github.com/WangXuan95/FPGA-USB-Device
#USB #HID #MSD #UVC #CDC #device #verilog
@ipcores
π₯15π10
An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
In this work, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured.
Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC.
The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3.
Links:
πΎ https://github.com/LukiLeu/FPGA_ADC
π https://dl.acm.org/doi/10.1145/3431920.3439287
#ADC #VHDL #TDC
@ipcores
In this work, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured.
Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC.
The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3.
Links:
πΎ https://github.com/LukiLeu/FPGA_ADC
π https://dl.acm.org/doi/10.1145/3431920.3439287
#ADC #VHDL #TDC
@ipcores
π₯20π9β€1
Send video/audio over HDMI on an FPGA
SystemVerilog code for HDMI 1.4b video/audio output on an FPGA.
Features
β«οΈ 24-bit color
β«οΈ Data island packets
β«οΈ Null packet
β«οΈ ECC with BCH systematic encoding GF(2^8)
β«οΈ Audio clock regeneration
β«οΈ L-PCM audio 2-channel
β«οΈ Audio InfoFrame
β«οΈ Video formats 1, 2, 3, 4, 16, 17, 18, 19
β«οΈ VGA text mode
β«οΈ IBM 8x16 font
β«οΈ Double Data Rate I/O (DDRIO)
β«οΈ Supports up to 3840x2160@30Hz
Links
πΎ https://github.com/hdl-util/hdmi
π https://purisa.me/blog/hdmi-released/
#HDMI #video #SV #SystemVerilog
@ipcores
SystemVerilog code for HDMI 1.4b video/audio output on an FPGA.
Features
β«οΈ 24-bit color
β«οΈ Data island packets
β«οΈ Null packet
β«οΈ ECC with BCH systematic encoding GF(2^8)
β«οΈ Audio clock regeneration
β«οΈ L-PCM audio 2-channel
β«οΈ Audio InfoFrame
β«οΈ Video formats 1, 2, 3, 4, 16, 17, 18, 19
β«οΈ VGA text mode
β«οΈ IBM 8x16 font
β«οΈ Double Data Rate I/O (DDRIO)
β«οΈ Supports up to 3840x2160@30Hz
Links
πΎ https://github.com/hdl-util/hdmi
π https://purisa.me/blog/hdmi-released/
#HDMI #video #SV #SystemVerilog
@ipcores
π₯10π5