Verilog Audio Controller is a basic audio controller providing I2S, SPDIF, and DAC outputs.
Simple to drive AXI4-L register interface, with built in 2048 entry buffer and interrupt on programmable threshold.
Features
β«οΈSPDIF tx supporting 16-bit data @ 44.1KHz or 48KHz
β«οΈI2S master (SCK, SDATA, WS)
β«οΈ2 channel sigma-delta DAC outputs
β«οΈAXI4-L register interface
β«οΈ8KB RAM buffer inferred (maps to BRAM)
β«οΈProgrammable interrupt threshold
β«οΈSingle interrupt output
https://github.com/ultraembedded/core_audio
#I2S #SPDIF #DAC #audio #verilog
@ipcores
Simple to drive AXI4-L register interface, with built in 2048 entry buffer and interrupt on programmable threshold.
Features
β«οΈSPDIF tx supporting 16-bit data @ 44.1KHz or 48KHz
β«οΈI2S master (SCK, SDATA, WS)
β«οΈ2 channel sigma-delta DAC outputs
β«οΈAXI4-L register interface
β«οΈ8KB RAM buffer inferred (maps to BRAM)
β«οΈProgrammable interrupt threshold
β«οΈSingle interrupt output
https://github.com/ultraembedded/core_audio
#I2S #SPDIF #DAC #audio #verilog
@ipcores
SURF (SLAC Ultimate RTL Framework) - a huge VHDL library for FPGA development.
Links:
β«οΈ sources
β«οΈ documentation
#VHDL #library #STL #primitives
@ipcores
Links:
β«οΈ sources
β«οΈ documentation
#VHDL #library #STL #primitives
@ipcores
A good entry point to CDC topic - from list of interesting documents explaining in depth CDC topics to gathering basic Clock domain crossing RTL modules, like:
β«οΈ IO debouncer
β«οΈ Simple synchronization thru 2 FFDs
β«οΈ Pulse synchronizer (with and w/o handshake)
β«οΈ Data bus synchronizer with recirculation mux
β«οΈ Asynchronous dual-clock FIFO (as submodule)
https://github.com/dpretet/cdc
#CDC #pulse #synchronizer #FF #fifo #SV #verilog
@ipcores
β«οΈ IO debouncer
β«οΈ Simple synchronization thru 2 FFDs
β«οΈ Pulse synchronizer (with and w/o handshake)
β«οΈ Data bus synchronizer with recirculation mux
β«οΈ Asynchronous dual-clock FIFO (as submodule)
https://github.com/dpretet/cdc
#CDC #pulse #synchronizer #FF #fifo #SV #verilog
@ipcores
π1
Full AXI VHDL verification model -
UVVM (the Open Source Universal VHDL Verification Methodology) has just released a free and open source VHDL verification model for AXI4. It can be accessible from UVVM repository and be used in any VHDL testbench - even inside an old legacy testbench if you like - or together with other VHDL verification systems.
The AXI4 model has full support for independent channels, burst transfers and out of order transmissons. The UVVM AXI4-lite has also been upgraded to allow independent channels. This means UVVM now provides free and open source VHDL verification models for AXI4, AXI4-lite and AXI4-stream.
#VHDL #UVVM #AXI #AMBA #BFM #verification
@ipcores
UVVM (the Open Source Universal VHDL Verification Methodology) has just released a free and open source VHDL verification model for AXI4. It can be accessible from UVVM repository and be used in any VHDL testbench - even inside an old legacy testbench if you like - or together with other VHDL verification systems.
The AXI4 model has full support for independent channels, burst transfers and out of order transmissons. The UVVM AXI4-lite has also been upgraded to allow independent channels. This means UVVM now provides free and open source VHDL verification models for AXI4, AXI4-lite and AXI4-stream.
#VHDL #UVVM #AXI #AMBA #BFM #verification
@ipcores
bladeRF-wiphy - project is an open-source IEEE 802.11 compatible software defined radio VHDL modem. The modem is able to modulate and demodulate 802.11 packets (the protocol WiFi is based on), and can be adapted to various FPGA SDR platforms.
Features:
β¦ IEEE 802.11 compatible FPGA based PHY receiver and transmitter
β¦ Linux mac80211 MAC integration
β¦ RX and TX monitor mode support
β¦ Hardware Distributed Coordination Function (DCF) allows quick turn-around time ACKs
β¦ High-performance equalizer β implements Zero Forcing (ZF) and optionally Decision Feedback Equalizer (DFE)
Links:
β¦ technical write-up
β¦ sources
#VHDL #OFDM #PHY #802.11 #BladeRF #WiFi
Features:
β¦ IEEE 802.11 compatible FPGA based PHY receiver and transmitter
β¦ Linux mac80211 MAC integration
β¦ RX and TX monitor mode support
β¦ Hardware Distributed Coordination Function (DCF) allows quick turn-around time ACKs
β¦ High-performance equalizer β implements Zero Forcing (ZF) and optionally Decision Feedback Equalizer (DFE)
Links:
β¦ technical write-up
β¦ sources
#VHDL #OFDM #PHY #802.11 #BladeRF #WiFi
π2
[WiP] ARM_Implementation - an implementation of ARM processor in Verilog.
Features:
β«οΈ Pipeline
β«οΈ Hazard Detection
β«οΈ Forwarding Unit
https://github.com/gsoosk/ARM_Implementation
#ARM #CPU #verilog
Features:
β«οΈ Pipeline
β«οΈ Hazard Detection
β«οΈ Forwarding Unit
https://github.com/gsoosk/ARM_Implementation
#ARM #CPU #verilog
[WiP] PCI2Nano - An open source FPGA PCI (not PCI-E) core, a 8250-Compatible PCI-based UART core and Nios II example design driving the UART.
Actually this is a turnkey set of open source design files and reference information for anyone to be able to start tinkering with PCI/PCIe on low end FPGAs. If you have a desire to interface to a host which supports PCIe and would like a quick way to design PCI functions which interface to the host, this project may be for you!
Links:
β«οΈ gateware
β«οΈ hardware
#PCI #verilog #UART #8250 #NIOS
Actually this is a turnkey set of open source design files and reference information for anyone to be able to start tinkering with PCI/PCIe on low end FPGAs. If you have a desire to interface to a host which supports PCIe and would like a quick way to design PCI functions which interface to the host, this project may be for you!
Links:
β«οΈ gateware
β«οΈ hardware
#PCI #verilog #UART #8250 #NIOS
π1
parser-gen - Network packet parser generator. This generator produces synthesizable SystemVerilog.
It generates both fixed and programmable parsers. Fixed parsers use a parse graph that is chosen at generation time, while programmable parsers use a parse graph that is chosen at run time. The logic in a fixed parser is generated specifically for the chosen parse graph. The logic in a programmable parser is independent of the parse graph; however, the parse graph is used to build the testbench and to populate the parse state table (emulated TCAM/RAM) module.
Links:
β«οΈ Documentation
β«οΈ Sources
#python #perl #sv #SystemVerilog #network #verification #tcp #udp #stimulus #tb
@ipcores
It generates both fixed and programmable parsers. Fixed parsers use a parse graph that is chosen at generation time, while programmable parsers use a parse graph that is chosen at run time. The logic in a fixed parser is generated specifically for the chosen parse graph. The logic in a programmable parser is independent of the parse graph; however, the parse graph is used to build the testbench and to populate the parse state table (emulated TCAM/RAM) module.
Links:
β«οΈ Documentation
β«οΈ Sources
#python #perl #sv #SystemVerilog #network #verification #tcp #udp #stimulus #tb
@ipcores
GitHub
parser-gen/README.parse-graphs.md at master Β· grg/parser-gen
Network packet parser generator. Contribute to grg/parser-gen development by creating an account on GitHub.
GLIP - The Generic Logic Interfacing Project.
GLIP is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a hardware component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 2.0, JTAG or TCP.
Features
β«οΈEasy FIFO-based communication, abstracting away all low-level details
β«οΈSupport for different communication channels through backends
β«οΈSide-channel communication (e.g. reset signals)
β«οΈDeveloped on and for Linux
Links:
β«οΈ Documentation
β«οΈ Sources
#verilog #SV #JTAG #FIFO #USB
@ipcores
GLIP is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a hardware component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 2.0, JTAG or TCP.
Features
β«οΈEasy FIFO-based communication, abstracting away all low-level details
β«οΈSupport for different communication channels through backends
β«οΈSide-channel communication (e.g. reset signals)
β«οΈDeveloped on and for Linux
Links:
β«οΈ Documentation
β«οΈ Sources
#verilog #SV #JTAG #FIFO #USB
@ipcores
Verilog LFSR - Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation.
β«οΈ
β«οΈ
β«οΈ
β«οΈ
β«οΈ
β«οΈ
Links:
β«οΈ Sources
#verilog #python #MyHDL #LFSR #CRC
@ipcores
β«οΈ
lfsr.v - Parametrizable combinatorial LFSR/CRC moduleβ«οΈ
lfsr_crc.v - Parametrizable CRC computation wrapperβ«οΈ
lfsr_descramble.v - Parametrizable LFSR self-synchronizing descramblerβ«οΈ
lfsr_prbs_check.v - Parametrizable PRBS checker wrapperβ«οΈ
lfsr_prbs_gen.v - Parametrizable PRBS generator wrapperβ«οΈ
lfsr_scramble.v - Parametrizable LFSR self-synchronizing scramblerLinks:
β«οΈ Sources
#verilog #python #MyHDL #LFSR #CRC
@ipcores
π1
SimpleVOut - FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See
Links:
β«οΈ Sources
#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
@ipcores
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See
svo_defines.vh for details on those parameters.Links:
β«οΈ Sources
#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
@ipcores
π1π1
Vortex - a full-system RISCV-based GPGPU processor.
Specs
β«οΈSupport RISC-V RV32I ISA
β«οΈFully scalable: 1 to 16 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/himanshu5-prog/vortexGPU
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
Specs
β«οΈSupport RISC-V RV32I ISA
β«οΈFully scalable: 1 to 16 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/himanshu5-prog/vortexGPU
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
π1
LoRa Modulator - a custom LoRa modulator that supports different bandwidths and spreading factors (SF) on Lattice ECP5 FPGA and I/Q interface with AT86RF215 RF radio.
πΎ https://github.com/uw-x/lora-modulator
#verilog #RF #LoRa #modulator #transmitter
@ipcores
πΎ https://github.com/uw-x/lora-modulator
#verilog #RF #LoRa #modulator #transmitter
@ipcores
XiangShan - mature (almost 6000 commits) high-performance RISC-V processor by Institute of Computing Technology, Chinese Academy of Sciences.
πΎ https://github.com/OpenXiangShan/XiangShan
π https://github.com/OpenXiangShan/XiangShan-doc
#ISA #RISCV #scala #chisel #CPU #FPU
@ipcores
πΎ https://github.com/OpenXiangShan/XiangShan
π https://github.com/OpenXiangShan/XiangShan-doc
#ISA #RISCV #scala #chisel #CPU #FPU
@ipcores
S-Link - a lightweight chiplet/chip-to-chip controller. S-Link is a simple, scalable, and flexible link controller protocol geared towards chiplets and chip-to-chip communication.
S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.
Features:
β«οΈMult-lane support (upto 128+)
β«οΈ128b/130b encoding
β«οΈParameterizable Application Data Widths
β«οΈConfigurable Attributes for fine tuning link controls and/or active link management
β«οΈECC/CRC for error checking of packet headers and payload data
β«οΈParameterizable pipeline stages to optimize for frequency and/or power
πΎ https://github.com/waviousllc/wav-slink-hw
#chiplet #protocol #verilog
@ipcores
S-Link defines the link layer, and gives freedom for various application and physical layers. The ultimate goal of S-Link is to provide a simple alternative for chiplet communication compared to other protocols.
Features:
β«οΈMult-lane support (upto 128+)
β«οΈ128b/130b encoding
β«οΈParameterizable Application Data Widths
β«οΈConfigurable Attributes for fine tuning link controls and/or active link management
β«οΈECC/CRC for error checking of packet headers and payload data
β«οΈParameterizable pipeline stages to optimize for frequency and/or power
πΎ https://github.com/waviousllc/wav-slink-hw
#chiplet #protocol #verilog
@ipcores
π5
700 followers π±
Thank you to everyone of you! ππ»
Thank you to everyone of you! ππ»
Vortex - a full-system RISCV-based GPGPU processor
Specs
β«οΈSupport RISC-V RV32IMF ISA
β«οΈFully scalable: 1 to 32 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/vortexgpgpu/vortex
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
Specs
β«οΈSupport RISC-V RV32IMF ISA
β«οΈFully scalable: 1 to 32 cores with optional L2 and L3 caches
β«οΈOpenCL 1.2 Support
β«οΈFPGA target: Intel Arria 10 @200 MHz
πΎ https://github.com/vortexgpgpu/vortex
#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores
π2β€1
Cryptography IP-cores lib
Used openSSL as reference models to check the correctness of the implementation.
Features:
β«οΈDES
β«οΈAES
β«οΈCTR-AES
β«οΈCBC-AES
β«οΈCBC-DES
β«οΈCBC-TDES
πΎ https://github.com/tmeissner/cryptocores
#Ρryptography #vhdl #verilog #aes #cipher #OSVVM
@ipcores
Used openSSL as reference models to check the correctness of the implementation.
Features:
β«οΈDES
β«οΈAES
β«οΈCTR-AES
β«οΈCBC-AES
β«οΈCBC-DES
β«οΈCBC-TDES
πΎ https://github.com/tmeissner/cryptocores
#Ρryptography #vhdl #verilog #aes #cipher #OSVVM
@ipcores
π3π₯1