A2I POWER Processor Core from IBM POWER team now open.
100% in pure VHDL

https://github.com/openpower-cores/a2i

#IBM #OpenPOWER #VHDL #FO4

FTDI FT601 SuperSpeed USB3.0 to AXI-Master allows an FT60x USB3.0 device to act as a high-performance AXI4 bus master.

Features:
◦ AXI-4 bus master with support for incrementing bursts and multiple outstanding transactions (for high performance)
◦ 2 x 8KB FIFO
◦ Designed to work @ 100MHz in FPGA (FT60x max clock rate)
◦ Uses FT60x 245 mode protocol (32-bit mode)

✅ AXI-4 burst reads @ 170MB/s
✅ AXI-4 burst writes @ 230MB/s

https://github.com/ultraembedded/core_ft60x_axi

#USB3 #USB #FT601 #AXI #verilog #host

AXI eMMC/SD Host Controller IP Core

Features:
◦ 4-bit SD card, 8-bit eMMC card mode
◦ 32-bit AXI Interface
◦ 50 MHz clock, Single Data Rate (SDR) | Double Data Rate (DDR)
◦ DMA support
◦ AutoCMD23 feature support
◦ Compatible with Linux Arasan SDHCI driver

link

#eMMC #SD #AXI #verilog

AMBA AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

◦ axi_atop_filter Filters atomic operations from AMBA5 (ATOPs)
◦ axi_burst_splitter Split AXI4 burst transfers into single-beat transactions
◦ axi_cdc AXI clock domain crossing based on a Gray FIFO implementation
◦ axi_cut Breaks all combinatorial paths between its input and output
◦ axi_delayer Synthesizable module which can (randomly) delays AXI channels
◦ axi_demux Demultiplexes an AXI bus from one slave port to multiple master ports
◦ axi_dw_converter A data width converter between AXI interfaces of any data width
◦ axi_dw_downsizer A data width converter between a wide AXI master and a narrower AXI slave
◦ axi_dw_upsizer A data width converter between a narrow AXI master and a wider AXI slave
◦ axi_err_slv Always responds with an AXI decode/slave error for transactions which are sent to it
◦ axi_id_prepend This module prepends/strips the MSB from the AXI IDs
◦ axi_intf This file defines the interfaces we support
◦ axi_isolate A module that can isolate downstream slaves from receiving new AXI4 transactions
◦ axi_join A connector that joins two AXI interfaces
◦ axi_lite_demux Demultiplexes an AXI4-Lite bus from one slave port to multiple master ports
◦ axi_lite_join A connector that joins two AXI-Lite interfaces
◦ axi_lite_mailbox A AXI4-Lite Mailbox with two slave ports and usage triggered irq
◦ axi_lite_mux Multiplexes AXI4-Lite slave ports down to one master port
◦ axi_lite_regs AXI4-Lite registers with optional read-only and protection features
◦ axi_lite_to_apb AXI4-Lite to APB4 protocol converter
◦ axi_lite_to_axi AXI4-Lite to AXI4 protocol converter
◦ axi_lite_xbar Fully-connected AXI4-Lite crossbar with an arbitrary number of slave and master ports
◦ axi_modify_address A connector that allows addresses of AXI requests to be changed
◦ axi_multicut AXI register which can be used to relax timing pressure on long AXI buses
◦ axi_mux Multiplexes the AXI4 slave ports down to one master port
◦ axi_pkg Contains AXI definitions, common structs, and useful helper functions
◦ axi_serializer Serializes transactions with different IDs to the same ID
◦ axi_test A set of testbench utilities for AXI interfaces
◦ axi_to_axi_lite AXI4 to AXI4-Lite protocol converter
◦ axi_xbar Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports

https://github.com/pulp-platform/axi

#AXI #verilog #NoC #interconnect #xbar #mailbox #burst

Corundum is an open-source, high-performance FPGA-based NIC

Features:
◦ 10G/25G/100G Ethernet
◦ PCI-E gen3
◦ HiPerf & tightly-integrated PCIe SG DMA engine
◦ MSI interrupts
◦ per-port transmit scheduling including high precision TDMA
◦ flow hashing
◦ checksum offloading
◦ native IEEE 1588 PTP timestamping

A Linux driver is included that integrates with the Linux networking stack. Development and debugging is facilitated by an extensive simulation framework that covers the entire system from a simulation model of the driver and PCI express interface on one side to the Ethernet interfaces on the other side.

https://github.com/ucsdsysnet/corundum

#NIC #verilog #MAC #10G #PTP #IEEE1588 #DMA #PCIE #TDMA #SFP #ETHERNET

A high performance streaming FFT core based on Bailey's 4-step large FFT algorithm (focused on speed optimizing: Fmax is up to 30% higher than Xilinx FFT IP)

Data input/output are continuous with no gaps between frames. Currently only supporting power-of-two sizes and fixed point data.

Top level VHDL code is generated by the script codegen/gen_fft.py.

https://github.com/owocomm-0/fpga-fft

#FFT #DSP #VHDL #generator #python #multicycle_path

Ariane CVA6 - an Application class 6-stage 64-bit RISC-V CPU capable of booting Linux.

CVA6 fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13.

It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.

https://github.com/openhwgroup/cva6

#ISA #RISCV #SystemVerilog #SV #CPU #RV64

Verilog Audio Controller is a basic audio controller providing I2S, SPDIF, and DAC outputs.
Simple to drive AXI4-L register interface, with built in 2048 entry buffer and interrupt on programmable threshold.

Features
▫️SPDIF tx supporting 16-bit data @ 44.1KHz or 48KHz
▫️I2S master (SCK, SDATA, WS)
▫️2 channel sigma-delta DAC outputs
▫️AXI4-L register interface
▫️8KB RAM buffer inferred (maps to BRAM)
▫️Programmable interrupt threshold
▫️Single interrupt output

https://github.com/ultraembedded/core_audio

#I2S #SPDIF #DAC #audio #verilog
@ipcores

SURF (SLAC Ultimate RTL Framework) - a huge VHDL library for FPGA development.

Links:
▫️ sources
▫️ documentation

#VHDL #library #STL #primitives
@ipcores

A good entry point to CDC topic - from list of interesting documents explaining in depth CDC topics to gathering basic Clock domain crossing RTL modules, like:
▫️ IO debouncer
▫️ Simple synchronization thru 2 FFDs
▫️ Pulse synchronizer (with and w/o handshake)
▫️ Data bus synchronizer with recirculation mux
▫️ Asynchronous dual-clock FIFO (as submodule)

https://github.com/dpretet/cdc

#CDC #pulse #synchronizer #FF #fifo #SV #verilog
@ipcores

Full AXI VHDL verification model -
UVVM (the Open Source Universal VHDL Verification Methodology) has just released a free and open source VHDL verification model for AXI4. It can be accessible from UVVM repository and be used in any VHDL testbench - even inside an old legacy testbench if you like - or together with other VHDL verification systems.

The AXI4 model has full support for independent channels, burst transfers and out of order transmissons. The UVVM AXI4-lite has also been upgraded to allow independent channels. This means UVVM now provides free and open source VHDL verification models for AXI4, AXI4-lite and AXI4-stream.


#VHDL #UVVM #AXI #AMBA #BFM #verification
@ipcores

VerCoLib-PCIe - The Versatile Communication Library is a collection of VHDL modules to enable DMA data transfer over PCIe.

◦ Doc
◦ Src

#PCIe #DMA #Xilinx #VHDL #Vivado #VUnit
@ipcores

bladeRF-wiphy - project is an open-source IEEE 802.11 compatible software defined radio VHDL modem. The modem is able to modulate and demodulate 802.11 packets (the protocol WiFi is based on), and can be adapted to various FPGA SDR platforms.

Features:
◦ IEEE 802.11 compatible FPGA based PHY receiver and transmitter
◦ Linux mac80211 MAC integration
◦ RX and TX monitor mode support
◦ Hardware Distributed Coordination Function (DCF) allows quick turn-around time ACKs
◦ High-performance equalizer – implements Zero Forcing (ZF) and optionally Decision Feedback Equalizer (DFE)

Links:
◦ technical write-up
◦ sources

#VHDL #OFDM #PHY #802.11 #BladeRF #WiFi

[WiP] ARM_Implementation - an implementation of ARM processor in Verilog.

Features:
▫️ Pipeline
▫️ Hazard Detection
▫️ Forwarding Unit

https://github.com/gsoosk/ARM_Implementation

#ARM #CPU #verilog

[WiP] PCI2Nano - An open source FPGA PCI (not PCI-E) core, a 8250-Compatible PCI-based UART core and Nios II example design driving the UART.

Actually this is a turnkey set of open source design files and reference information for anyone to be able to start tinkering with PCI/PCIe on low end FPGAs. If you have a desire to interface to a host which supports PCIe and would like a quick way to design PCI functions which interface to the host, this project may be for you!

Links:
▫️ gateware
▫️ hardware

#PCI #verilog #UART #8250 #NIOS

parser-gen - Network packet parser generator. This generator produces synthesizable SystemVerilog.

It generates both fixed and programmable parsers. Fixed parsers use a parse graph that is chosen at generation time, while programmable parsers use a parse graph that is chosen at run time. The logic in a fixed parser is generated specifically for the chosen parse graph. The logic in a programmable parser is independent of the parse graph; however, the parse graph is used to build the testbench and to populate the parse state table (emulated TCAM/RAM) module.

Links:
▫️ Documentation
▫️ Sources

#python #perl #sv #SystemVerilog #network #verification #tcp #udp #stimulus #tb
@ipcores

GLIP - The Generic Logic Interfacing Project.

GLIP is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a hardware component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 2.0, JTAG or TCP.

Features
▫️Easy FIFO-based communication, abstracting away all low-level details
▫️Support for different communication channels through backends
▫️Side-channel communication (e.g. reset signals)
▫️Developed on and for Linux

Links:
▫️ Documentation
▫️ Sources

#verilog #SV #JTAG #FIFO #USB
@ipcores

Verilog LFSR - Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation.

▫️lfsr.v - Parametrizable combinatorial LFSR/CRC module
▫️lfsr_crc.v - Parametrizable CRC computation wrapper
▫️lfsr_descramble.v - Parametrizable LFSR self-synchronizing descrambler
▫️lfsr_prbs_check.v - Parametrizable PRBS checker wrapper
▫️lfsr_prbs_gen.v - Parametrizable PRBS generator wrapper
▫️lfsr_scramble.v - Parametrizable LFSR self-synchronizing scrambler

Links:
▫️ Sources

#verilog #python #MyHDL #LFSR #CRC
@ipcores

FPU Generator - a Floating Point Adder/Multiplier/Multiply-Accumulate generator and testbench.

Links:
▫️ Sources

#perl #matlab #FPU #FloatingPoint
@ipcores

SimpleVOut - FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

Links:
▫️ Sources

#verilog #AXIS #VGA #DVI #HDMI #OpenLDI
@ipcores

Vortex - a full-system RISCV-based GPGPU processor.

Specs
▫️Support RISC-V RV32I ISA
▫️Fully scalable: 1 to 16 cores with optional L2 and L3 caches
▫️OpenCL 1.2 Support
▫️FPGA target: Intel Arria 10 @200 MHz

💾 https://github.com/himanshu5-prog/vortexGPU

#verilog #GPGPU #GPU #FPGA #LLVM
@ipcores