ScopeIO - Embedded Measurement System in the FPGA that lets you see as much data as you need using as few resources as possible.

Features:
◦ Small footprint to embed it
◦ Portability
◦ VGA to display data
◦ BRAM requirement only
◦ DDR core to capture high speed data
◦ UDP to communicate with host

Links:
◦ sources
◦ docs
◦ slides

#debug #simulation #VHDL #oscilloscope

MIPI CSI Camera Sensor Receiver implementation. Tested with IMX219 on Lattice MachXO3LF.

https://github.com/circuitvalley/mipi_csi_receiver_FPGA

#MIPI #CSI #video #verilog

MIPI DSI Bridge: Controller Firmware code receiving images from PC (over USB) and transmitting over SPI to FPGA. Tested with LH154Q01-TD01 LCD 240x240 1.54 inch (Apple IPOD nano 6G) on Lattice MachXO3LF.

◦ sources
◦ description

#MIPI #DSI #video #verilog

DVB_FPGA - RTL implementation of components for DVB-S2 (initially focusing on the transmission side).

Features:
◦ AXI-Stream interfaces
◦ Frame types: Normal and short
◦ Constellations: 8 PSK, 16 APSK and 32 APSK
◦ Code rates: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10

Components done:
◦ Baseband scrambler
◦ BCH encoder
◦ Bit interleaver
Components todo:
◦ Constellation mapper
◦ LDPC Encoder
◦ Physical layer framing

https://github.com/phase4ground/dvb_fpga

#VHDL #DVB #AXI #LDPC

Ibex - a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.

Ibex is ideally suited as control core in many embedded scenarios. Ibex is a high-quality core: together with the RTL, lowRISC provides full UVM-based verification, extensive documentation and all the tools to successfully integrate Ibex into designs.

Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.

◦ Sources
◦ Docs

#ISA #RISCV #SystemVerilog #SV #CPU #LowRISC

FastVDMA - fast, vendor-neutral DMA IP in Chisel. This DMA controller designed with portability and customizability in mind.

The purpose of a DMA controller is to arbitrate and handle the transfer of blocks of data directly from an I/O device to the main memory of a system, with minimal intervention of the CPU.

The main feature of FastVDMA is the ability to support multiple types of buses, namely AXI4, AXI-Stream and Wishbone. Each one of these buses can be used as write or read frontends.

Features:
◦ Interrupts
◦ 2D transfers with configurable stride
◦ External frame synchronization inputs

Links:
◦ Description
◦ Sources

#DMA #chisel #AXI #wishbone

FPGA USB Bootloader - an open source IP for programming FPGAs without extra USB interface chips.

It implements a USB virtual serial port to SPI flash bridge on the FPGA fabric itself. For FPGAs that support loading multiple configurations it is possible for the bootloader to be completely unloaded from the FPGA before the user configuration is loaded in. From the host computer's perspective, the bootloader looks like a serial port.

Links:
◦ Device side
◦ Host side

#USB #bootloader #FPGA #verilog

Lightweigth USB Core - core that would be similar to the SIE you find in classic microcontrollers that support USBs. That means it requires a soft core to implement the actual USB stack, the hardware itself only handle up to the transaction layer of USB.

It's designed to be small but still allow full flexibility of what kind of device it implements, supports all types of transfers, all packet sizes and any combination of end points without having to change the hardware configuration at all.

Features:
◦ 10 BRAM, 390 FF and 530 LUT4
◦ Clocked at 48 MHz
◦ Wishbone interface for the CSRs and Buffer Descriptors

Links:
◦ Doc
◦ Src

#USB #iCE40 #FPGA #verilog #PHY

MIPI I3C Basic v1.0 - implementation of I3C Slave in Verilog with BSD license to support use in sensors and other devices.

Features:
◦ I3C SDR protocol
◦ All required CCCs plus some optional ones
◦ IBI (in band interrupt) including optional IBI data byte
◦ Support for I2C with a static address
◦ Two different integrations depending on system:
◦ Full APB memory mapped registers for processor based systems
◦ Autonomous model for state machine ASICs

Note: this version does not include HDR-DDR, HDR-Ternary, Time-control, nor Master support. It also lacks some other advanced features including for i2c.

https://github.com/NXP/i3c-slave-design

#I3C #I2C #verilog #MIPI

Verilog PCI-Express Components

Collection of PCI express related components. Includes PCIe to AXI and AXI lite bridges, a simple PCIe AXI DMA engine, and a flexible, high-performance DMA subsystem. Currently supports operation with the Xilinx Ultrascale and Ultrascale+ PCIe hard IP cores with interfaces between 64 and 512 bits. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

◦ Doc
◦ Src

#PCIE #verilog #MyHDL #AXI #BFM #xilinx #DMA

Piplined FFT Core - configurable C++ generator of Verilog FFT cores.

The FFT generated by this project is very configurable. By simple adjustment of a command line parameter, the FFT created will either be a forward FFT or an inverse FFT. The number of bits processed, kept, and maintained by this FFT are also configurable. Even the number of bits used for the twiddle factors, or whether or not to bit reverse the outputs, are all configurable parts to this FFT core.

https://github.com/ZipCPU/dblclockfft

#DSP #FFT #generator #verilog

A2I POWER Processor Core from IBM POWER team now open.
100% in pure VHDL

https://github.com/openpower-cores/a2i

#IBM #OpenPOWER #VHDL #FO4

FTDI FT601 SuperSpeed USB3.0 to AXI-Master allows an FT60x USB3.0 device to act as a high-performance AXI4 bus master.

Features:
◦ AXI-4 bus master with support for incrementing bursts and multiple outstanding transactions (for high performance)
◦ 2 x 8KB FIFO
◦ Designed to work @ 100MHz in FPGA (FT60x max clock rate)
◦ Uses FT60x 245 mode protocol (32-bit mode)

✅ AXI-4 burst reads @ 170MB/s
✅ AXI-4 burst writes @ 230MB/s

https://github.com/ultraembedded/core_ft60x_axi

#USB3 #USB #FT601 #AXI #verilog #host

AXI eMMC/SD Host Controller IP Core

Features:
◦ 4-bit SD card, 8-bit eMMC card mode
◦ 32-bit AXI Interface
◦ 50 MHz clock, Single Data Rate (SDR) | Double Data Rate (DDR)
◦ DMA support
◦ AutoCMD23 feature support
◦ Compatible with Linux Arasan SDHCI driver

link

#eMMC #SD #AXI #verilog

AMBA AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

◦ axi_atop_filter Filters atomic operations from AMBA5 (ATOPs)
◦ axi_burst_splitter Split AXI4 burst transfers into single-beat transactions
◦ axi_cdc AXI clock domain crossing based on a Gray FIFO implementation
◦ axi_cut Breaks all combinatorial paths between its input and output
◦ axi_delayer Synthesizable module which can (randomly) delays AXI channels
◦ axi_demux Demultiplexes an AXI bus from one slave port to multiple master ports
◦ axi_dw_converter A data width converter between AXI interfaces of any data width
◦ axi_dw_downsizer A data width converter between a wide AXI master and a narrower AXI slave
◦ axi_dw_upsizer A data width converter between a narrow AXI master and a wider AXI slave
◦ axi_err_slv Always responds with an AXI decode/slave error for transactions which are sent to it
◦ axi_id_prepend This module prepends/strips the MSB from the AXI IDs
◦ axi_intf This file defines the interfaces we support
◦ axi_isolate A module that can isolate downstream slaves from receiving new AXI4 transactions
◦ axi_join A connector that joins two AXI interfaces
◦ axi_lite_demux Demultiplexes an AXI4-Lite bus from one slave port to multiple master ports
◦ axi_lite_join A connector that joins two AXI-Lite interfaces
◦ axi_lite_mailbox A AXI4-Lite Mailbox with two slave ports and usage triggered irq
◦ axi_lite_mux Multiplexes AXI4-Lite slave ports down to one master port
◦ axi_lite_regs AXI4-Lite registers with optional read-only and protection features
◦ axi_lite_to_apb AXI4-Lite to APB4 protocol converter
◦ axi_lite_to_axi AXI4-Lite to AXI4 protocol converter
◦ axi_lite_xbar Fully-connected AXI4-Lite crossbar with an arbitrary number of slave and master ports
◦ axi_modify_address A connector that allows addresses of AXI requests to be changed
◦ axi_multicut AXI register which can be used to relax timing pressure on long AXI buses
◦ axi_mux Multiplexes the AXI4 slave ports down to one master port
◦ axi_pkg Contains AXI definitions, common structs, and useful helper functions
◦ axi_serializer Serializes transactions with different IDs to the same ID
◦ axi_test A set of testbench utilities for AXI interfaces
◦ axi_to_axi_lite AXI4 to AXI4-Lite protocol converter
◦ axi_xbar Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports

https://github.com/pulp-platform/axi

#AXI #verilog #NoC #interconnect #xbar #mailbox #burst

Corundum is an open-source, high-performance FPGA-based NIC

Features:
◦ 10G/25G/100G Ethernet
◦ PCI-E gen3
◦ HiPerf & tightly-integrated PCIe SG DMA engine
◦ MSI interrupts
◦ per-port transmit scheduling including high precision TDMA
◦ flow hashing
◦ checksum offloading
◦ native IEEE 1588 PTP timestamping

A Linux driver is included that integrates with the Linux networking stack. Development and debugging is facilitated by an extensive simulation framework that covers the entire system from a simulation model of the driver and PCI express interface on one side to the Ethernet interfaces on the other side.

https://github.com/ucsdsysnet/corundum

#NIC #verilog #MAC #10G #PTP #IEEE1588 #DMA #PCIE #TDMA #SFP #ETHERNET

A high performance streaming FFT core based on Bailey's 4-step large FFT algorithm (focused on speed optimizing: Fmax is up to 30% higher than Xilinx FFT IP)

Data input/output are continuous with no gaps between frames. Currently only supporting power-of-two sizes and fixed point data.

Top level VHDL code is generated by the script codegen/gen_fft.py.

https://github.com/owocomm-0/fpga-fft

#FFT #DSP #VHDL #generator #python #multicycle_path

Ariane CVA6 - an Application class 6-stage 64-bit RISC-V CPU capable of booting Linux.

CVA6 fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore it is compliant to the draft external debug spec 0.13.

It has configurable size, separate TLBs, a hardware PTW and branch-prediction (branch target buffer and branch history table). The primary design goal was on reducing critical path length.

https://github.com/openhwgroup/cva6

#ISA #RISCV #SystemVerilog #SV #CPU #RV64

Verilog Audio Controller is a basic audio controller providing I2S, SPDIF, and DAC outputs.
Simple to drive AXI4-L register interface, with built in 2048 entry buffer and interrupt on programmable threshold.

Features
▫️SPDIF tx supporting 16-bit data @ 44.1KHz or 48KHz
▫️I2S master (SCK, SDATA, WS)
▫️2 channel sigma-delta DAC outputs
▫️AXI4-L register interface
▫️8KB RAM buffer inferred (maps to BRAM)
▫️Programmable interrupt threshold
▫️Single interrupt output

https://github.com/ultraembedded/core_audio

#I2S #SPDIF #DAC #audio #verilog
@ipcores

SURF (SLAC Ultimate RTL Framework) - a huge VHDL library for FPGA development.

Links:
▫️ sources
▫️ documentation

#VHDL #library #STL #primitives
@ipcores